SI53301 Datasheet, PDF (26/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
3. Pin Description: 32-Pin QFN
DIVA 1
SFOUTA[1] ²
SFOUTA[0] ³
Q0 ⁴
Q0 ⁵
GND ⁶
V_DD
7
CLK_SEL 8
GND
PAD
24 DIVB
23 SFOUTB[1]
22 SFOUTB[0]
21 _Q5
20 _Q5
19 _VDDOB
18 _VDDOA
17 _VREF
Table 21. Pin Description
Pin
Name
Type*
Description
1
DIVA
I Output divider control pin for Bank A (Outputs: Q0 to Q2)
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
2 SFOUTA[1]
I Output signal format control pin for Bank A (Outputs: Q0 to Q2)
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
3 SFOUTA[0]
I Output signal format control pin for Bank A (Outputs: Q0 to Q2)
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
4
Q0
O Output clock 0 (complement)
5
Q0
O Output clock 0
6
GND
GND Ground
7
V_DD
P Core voltage supply.
Bypass with 1.0 µF capacitor and place as close to the V_DD pin as possible.
26
Rev. 1.1