SI53301 Datasheet, PDF (16/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
2.5. Glitchless Clock Input Switching
The Si53301 features glitchless switching between two valid input clocks. Figure 7 illustrates that switching
between input clocks does not generate runt pulses or glitches at the output.
CLK1
CLK0
CLK_SEL
Note 1
Note 2
Note 3
Qn
Notes:
1. Q_n continues with CLK0 for 2-3 falling edges of CLK0.
2. Q_n is disabled low for 2-3 falling edges of CLK1 .
3. Q_n starts on the first rising edge after 1 + 2.
Figure 7. Glitchless Input Clock Switch
The Si53301 supports glitchless switching between clocks at the same frequency. In addition, the device supports
glitchless switching between 2 input clocks that are up to 10x different in frequency. When a switchover to a new
clock is made, the output will disable low after two or three clock cycles of the previously-selected input clock. The
outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start
from the newly-selected input. In the case a switchover to an absent clock is made, the output will glitchlessly stop
low and wait for edges of the newly selected clock. A switchover from an absent clock to a live clock will also be
glitchless. Note that the CLK_SEL input should not be toggled faster than 1/250th the frequency of the slower input
clock.
2.6. Synchronous Output Enable
The Si53301 features a synchronous output enable (disable) feature. The output enable pin is sampled and
synchronized to the falling edge of the input clock. This feature prevents runt pulses from being generated when
the outputs are enabled or disabled.
When OE is low, Q is held low and Q is held high for differential output formats. For LVCMOS output format
options, both Q and Q are held low when OE is set low. The device outputs are enabled when the output enable pin
is unconnected. See Table 10, “AC Characteristics,” on page 6 for output enable and output disable times.
2.7. Flexible Output Divider
The Si53301 provides optional clock division in addition to clock distribution. The divider setting for each bank of
output clocks is selected via 3-level control pins as shown in the table below. Leaving the DIVx pins open will force
a divider value of 1 which is the default mode of operation. Note that when using the on-chip clock divider, a
minimum input clock slew rate of 30 mV/ns is required.
Table 18. Post Divider Selection
DIVx
Divider Value
Open*
1 (default)
0
2
1
4
*Note: DIVx are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting.
When left open, the pin floats to VDD/2.
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Rev. 1.1