SI53301 Datasheet, PDF (27/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
Table 21. Pin Description (Continued)
Pin
Name
Type*
Description
8
CLK_SEL
I Mux input select pin:
Clock inputs are switched without the introduction of glitches.
When CLK_SEL is high, CLK1 is selected.
When CLK_SEL is low, CLK0 is selected.
CLK_SEL contains an internal pull-down resistor.
9
LOS0
O The LOS0 status pin indicates whether a clock is present at the CLK0 pin:
CLK0 input clock present LOS0 = 0
CLK0 input clock not present LOS0 = 1
10
CLK0
I Input clock 0
11
CLK0
I Input clock 0 (complement).
12
OEA
13
OEB
14
CLK1
15
CLK1
I Output enable—Bank A (Outputs: Q0 to Q2)
When OE = high, the Bank A outputs are enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OEA features an internal pull-up resistor and may be left unconnected.
I Output enable—Bank B (Outputs: Q3 to Q5)
When OE = high, the Bank B outputs are enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OEB features an internal pull-up resistor and may be left unconnected.
I Input clock 1
I Input clock 1 (complement)
16
LOS1
17
V_REF
18
V_DDOA
19
V_DDOB
20
Q5
O The LOS1 status pin indicates whether a clock is present at the CLK1 pin:
CLK1 input clock present LOS1 = 0
CLK1 input clock not present LOS1 = 1
O Input clock reference voltage used to bias CLK0 or CLK1 clock input pins. VREF is
required when a differential input clock is applied to the device and terminated as
a single-ended reference. VREF may be left unconnected for LVCMOS or differen-
tial clock inputs. See section “2.3. Input Clock Voltage Reference (VREF)” for
details.
P Output voltage supply—Bank A (Outputs: Q0 to Q2)
Bypass with 1.0 µF capacitor and place as close to the V_DDOA pin as
possible.
P Output voltage supply—Bank B (Outputs: Q3 to Q5)
Bypass with 1.0 µF capacitor and place as close to the V_DDOB pin as
possible.
O Output clock 5 (complement)
21
Q5
O Output clock 5
Rev. 1.1
27