SI53301 Datasheet, PDF (6/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
Table 8. Output Characteristics—LVCMOS
(V_DDOX = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Output Voltage High^* V_OH
0.75 x V_DDOX
—
—
Output Voltage Low^*
V_OL
—
—
0.25 x V_DDOX
*Note: I_OH and I_OL per the Output Signal Format Table for specific V_DDOX and SFOUTX settings.
Unit
V
V
Table 9. Output Characteristics—HCSL
(V_DDOX = 3.3 V ± 10%, T_A = –40 to 85 °C))
Parameter
Output Voltage High
Output Voltage Low
Single-Ended
Output Swing
Crossing Voltage
Symbol
V_OH
V_OL
V_SE
V_C
Test Condition
R_L = 50 Ω to GND
R_L = 50 Ω to GND
R_L = 50 Ω to GND
R_L = 50 Ω to GND
Min
Typ
Max
Unit
550
700
900
mV
–150
0
150
mV
550
700
850
mV
250
350
550
mV
Table 10. AC Characteristics
(V_DD = V_DDOX = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
LOSx Clear Time
Symbol
T_LOSCLR
Test Condition
F < 100 MHz
F > 100 MHz
Min Typ Max Unit
— Tper+15 —
ns
—
25
—
ns
LOSx Activation Time
Frequency
T_LOSACT
—
F LVPECL, low power LVPECL, LVDS, 1
CML, HCSL
15
—
µs
—
725 MHz
LVCMOS
1
—
200 MHz
Duty Cycle
D_C
200 MHz, 20/80%T_R/T_F<10% of
40
50
60
%
Note: 50% input duty cycle.
period (LVCMOS)
(12 mA drive)
20/80% T_R/T_F<10% of period
(Differential)
48
50
52
%
Notes:
1. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required.
2. HCSL measurements were made with receiver termination. See Figure 9 on page 19.
3. Output to Output skew specified for outputs with an identical configuration.
4. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
5. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DDOX (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
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Rev. 1.1