SI53301 Datasheet, PDF (33/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 1.0
Front Page
 Updates functional block diagram and pin
assignment figures to add LOS pins.
Recommended Operating Conditions
 Updated Table 1 to clarify notation.
 Spec change: HCSL is supported at 3.3 V only.
Input Clock Specifications Table
 Clarification: Input swing spec clarified applies to
differential input.
 Clarification: Input voltage high/low spec is for
LVCMOS input.
 Clarification: Input capacitance with respect to GND.
DC Common Characteristics Table
 Clarification: Denote frequencies for S.E. and
Differential outputs for current consumption specs.
 Spec change: Updated Supply/output buffer supply
current specs.
 Spec change: LVCMOS is not supported at 1.8 V.
 Spec change: Input high/low voltage levels.
 Correction to show which signals use internal pull-
up/pull-down.
 Added specification: Output voltage high/low to
support added LOS feature.
Output Voltage Specifications
 Spec change: LVPECL and Low-Power LVPECL
output voltage level specifications changes.
 Spec change: LVPECL and low-power LVPECL DC
characteristics separated into two tables.
 Spec change: LVCMOS logic levels improved.
 Spec change: HCSL single-ended output swing max/
min added.
AC Characteristics
 Ouput rise/fall time spec test conditions, added low-
power LVPECL.
 Duty cycle spec added for LVCMOS, updated
differential spec and test conditions.
 Spec change: Propagation delay (was TBD)
 Spec change: Added/expanded output enable/
disable time specs for three frequencies.
 Spec change: part to part skew updated.
 Spec chnage: Power supply noise rejection updated.
 Spec change: Improved additive Jitter specification.
 Spec change: Output to output skew updated.
 Updated footnotes.
Additive Jitter, Differential Clock Input Table
 Spec changes: Table changed to provide improved
specs and add spec previously "TBD" based upon
differential measurements.
 Added footnote and test setup Figure 1 for clarity.
Additive Jitter, Single-Ended Clock Input Table
 Spec changes: Table changed to provide improved
specs and add specs previously "TBD" based upon
differential measurements.
 Added footnote and test setup Figure 1 for clarity.
Pinout Description
 No pin assignments were moved. Two pins
previously indicated as NC have been assigned to
the LOS function as follows: Pin 9 is LOS0 and Pin
16 is LOS1.
 Pin assignment and descriptions have been edited
to reflect this added feature's pin assignment.
 Correction: Top Marking spec/explanation have been
corrected.
Other Changes
 Added Figure 1 test setup.
 Input format change: 1.8 V LVCMOS is not
supported.
 Clarified support for HCSL is at 3.3 V.
 Updated recommendation in Figure 3 for optimal
performance.
 Added dc-coupled receiver termination scheme.
 Output format Selection table reflects LVCMOS (no
1.8 V) and HCSL (3.3 V only).
 Loss of Signal feature is added. Section to describe
the loss of signal indicator feature.
 Output termination recommendations: updated to
show Low-power LVPECL supported termination.
 Correction: LVCMOS series termination
recommendation table.
 Typical phase noise plots updated with improved
figures and clearer results.
Revision 1.0 to Revision 1.1
Added additional information to clarify the use of the
voltage reference feature.
Added pin type description to the pinout table
Added low-voltage termination options for 1.2 V and
1.5 V LVCMOS support
Improved and more detailed performance
specifications
Clarification of output clock bank A and bank B
assignments
Correction to front-page buffer block diagram
Rev. 1.1
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