SI53301 Datasheet, PDF (28/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
Table 21. Pin Description (Continued)
Pin
Name
Type*
Description
22 SFOUTB[0]
23 SFOUTB[1]
24
DIVB
25
Q4
I Output signal format control pin for Bank B (Outputs: Q3 to Q5).
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
I Output signal format control pin for Bank B (Outputs: Q3 to Q5).
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
I Output divider control pin for Bank B (Outputs: Q3 to Q5).
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
O Output clock 4 (complement)
26
Q4
O Output clock 4
27
Q3
28
Q3
29
Q2
O Output clock 3 (complement)
O Output clock 3
O Output clock 2 (complement)
30
Q2
31
Q1
O Output clock 2
O Output clock 1 (complement)
32
Q1
O Output clock 1
GND
Pad
GND
GND Ground Pad.
Power supply ground and thermal relief.
*Pin types are: I = input, O = output, P = power, GND = ground.
28
Rev. 1.1