SI53301 Datasheet, PDF (1/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX
Features
 6 differential or 12 LVCMOS outputs  Loss of signal (LOS) monitors for
 Ultra-low additive jitter: 45 fs rms
loss of input clock
 Wide frequency range: 1 to 725 MHz ^{ Independent V}_DD ^{and V}_DDO ^:
 Universal any-format input with pin
1.8/2.5/3.3 V
selectable output formats
 1.2/1.5 V LVCMOS output support
 LVPECL, low power LVPECL, LVDS,  Selectable LVCMOS drive strength to
CML, HCSL, LVCMOS
tailor jitter and EMI performance
 2:1 input mux
 Small size: 32-QFN (5 mm x 5 mm)
 Glitchless input clock switching
 RoHS compliant, Pb-free
 Synchronous output enable
 Industrial temperature range:
 Output clock division: /1, /2, /4
–40 to +85 °C
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Description
The Si53301 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and divider selection. The Si53301 features a 2:1 input
mux with glitchless switching, making it ideal for redundant clocking applications.
The Si53301 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53301 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments. Independent core and output bank supply pins provide
integrated level translation without the need for external circuitry.
Functional Block Diagram
Ordering Information:
See page 29.
Pin Assignments
Si53301
DIVA 1
SFOUTA[1] ²
SFOUTA[0] 3
Q0 ⁴
Q0 ⁵
GND ⁶
VDD
7
CLK_SEL 8
GND
PAD
24 DIVB
23 SFOUTB[1]
22 SFOUTB[0]
21 Q5
20 Q5
19 _VDDOB
18 V_DDOA
17 _VREF
Patents pending
Vref
LOS0
LOS1
CLK0
/CLK0
CLK1
/CLK1
CLK_SEL
VDD
Vref
Generator
LOS
Monitor
Power
Supply
Filtering
DivA
BANK A
Switching
Logic
DivB
BANK B
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2
/Q0, /Q1, /Q2
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q3, Q4, Q5
/Q3, /Q4, /Q5
Rev. 1.1 6/14
Copyright © 2014 by Silicon Laboratories
Si53301