SI53019-A01A Datasheet, PDF (8/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53019-A01A
Table 5. Clock Input Parameters
T_A = 0–70 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Input High Voltage
Input Low Voltage
Input Common Mode
Voltage
Input Amplitude
Input Slew Rate
Input Duty Cycle
Input Jitter—Cycle to
Cycle
Input Frequency
Input SS Modulation
Rate
Symbol
V_IHDIF
V_IHDIF
V_com
Test Condition
Differential Inputs
(singled-ended measurement)
Differential Inputs
(singled-ended measurement)
Common mode input voltage
V_swing
dv/dt
J_DFin
Peak to Peak Value
Measured differentially
Measurement from differential wave
form
Differential measurement
F_ibyp
F_iPLL
FiPLL
f_MODIN
V_DD = 3.3 V, bypass mode
V_DD = 3.3 V, 100 MHz PLL Mode
V_DD = 3.3 V, 133.33 MHz PLL Mode
Triangle Wave modulation
Min Typ Max
600 800 1150
Vss-300 0
300
300
— 1000
300
— 1450
0.4
—
8
45
50
55
—
—
125
33
—
150
90
100 110
120 133.33 147
30
31.5
33
Unit
mV
mV
mV
mV
V/ns
%
ps
MHz
MHz
MHz
kHz
8
Rev. 1.3