SI53019-A01A Datasheet, PDF (13/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

2. Functional Description
Si53019-A01A
OE(5_12)
8
FB_IN
FB_IN
CLK_IN
CLK_IN
100M_133
HBW_BYPASS_LBW
SA_0
SA_1
PWRGD / PWRDN
SDA
SCL
SSC Compatible
PLL
Control
Logic
FB_OUT
DIF_[18:0]
IREF
Figure 1. Si53019-A01A Functional Block Diagram
Table 11. Functionality at Power Up (PLL Mode)
100M_133M
1
0
CLK_IN
(MHz)
100
133.33
Conditions
CLK_IN
CLK_IN
Table 12. PLL Operating Mode Readback Table
HBW_BYPASS_LBW Byte 0, Bit 7 Byte 0, Bit 6
Low
0
0
Mid (Bypass)
0
1
High
1
1
Mode
PLL Low BW
Bypass
PLL High BW
Rev. 1.3
13