SI53019-A01A Datasheet, PDF (28/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53019-A01A
Table 30. Si53019-A01A 72-Pin QFN Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
Type
Description
VDDA
3.3 V 3.3 V power supply for PLL.
GNDA
GND Ground for PLL.
IREF
100M_133M
HBW_BYPASS_LBW
PWRGD/PWRDN
OUT
This pin establishes the reference for the differential current mode output
pairs. It requires a fixed precision resistor to ground. 475  is the
standard value for 100  differential impedance. Other impedances
require different values.
I,SE 3.3 V tolerant inputs for input/output frequency selection. An external pull-
up or pull-down resistor is attached to this pin to select the input/output
frequency.
High = 100 MHz output
Low = 133 MHz output
I, SE
Tri-Level input for selecting the PLL bandwidth or bypass mode.
High = High BW mode
Med = Bypass mode
Low = Low BW mode
I 3.3 V LVTTL input to power up or power down the device.
GND
GND Ground for outputs.
VDDR
CLK_IN
VDD 3.3 V power supply for differential input receiver. This VDDR should be
treated as an analog power rail and filtered appropriately.
I, DIF 0.7 V Differential TRUE input.
CLK_IN
I, DIF 0.7 V Differential input.
SA_0
I,PU 3.3 V LVTTL input selecting the address. Tri-level input.
SDA
I/O Open collector SMBus data.
SCL
I/O SMBus slave clock input.
SA_1
I,PU 3.3 V LVTTL input selecting the address. Tri-level input.
FB_IN
FB_IN
FB_OUT
FB_OUT
DIF_0
I/O True differential feedback input. Provides feedback signal to the PLL for
synchronization with the input clock to eliminate phase error.
I/O Complementary differential feedback input. Provides feedback signal to
the PLL for synchronization with the input clock to eliminate phase error.
I/O Complementary differential feedback output, provides feedback signal to
the PLL for synchronization with input clock to eliminate phase error.
I/O True differential feedback output, provides feedback signal to the PLL for
synchronization with the input clock to eliminate phase error.
O, DIF 0.7 V Differential TRUE clock output.
DIF_0
O, DIF 0.7 V Differential Complimentary clock output.
VDD
VDD Power supply for differential outputs.
DIF_1
O, DIF 0.7 V Differential TRUE clock output.
28
Rev. 1.3