SI53019-A01A Datasheet, PDF (14/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53019-A01A
Table 13. Tri-Level Input Thresholds
Parameter
Low
Mid
High
Voltage
<0.8 V
1.2<Vin<1.8 V
Vin>2.2 V
Table 14. Power Connections
Pin Number
Description
V_DD
GND
1
2
Analog PLL
8
7
Analog Input
21,31,45,58,68
26,44,63
DIF Outputs
Note: T_A = 0–70 °C; supply voltage V_DD = 3.3 V ±5%
Table 15. SMBus Addressing
Pin
SMBus Address
SMB_A1
SMB_A0
0
0
D8
0
M
DA
0
1
DE
M
0
C2
M
M
C4
M
1
C6
1
0
CA
1
M
CC
1
1
CE
14
Rev. 1.3