SI53019-A01A Datasheet, PDF (12/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53019-A01A
Table 8. Clock Periods Differential Clock Outputs with SSC Disabled
SSC OFF
Measurement Window
Unit
Center
Freq, MHz ^{1 Clock}
1 µs
0.1 s
0.1 s
0.1 s
1 µs
1 Clock
-C-C Jitter -SSC
-ppm
0 ppm
+ppm
+SSC
+C-C
AbsPer Short
Long
Period
Long
Short
Jitter
Min Term AVG Term AVG Nominal Term AVG Term AVG AbsPer
Min
Min
Max
Max
Max
100.00 9.94900
9.99900 10.00000 10.00100
10.05100
ns
133.33 7.44925
7.49925 7.50000 7.50075
7.55075
ns
Table 9. Clock Periods Differential Clock Outputs with SSC Enabled
SSC ON
Measurement Window
Unit
Center
Freq, MHz ^{1 Clock}
1 µs
0.1 s
0.1 s
0.1 s
1 µs
1 Clock
-C-C
-SSC
-ppm
0 ppm
+ppm
+SSC
+C-C
Jitter
Short
Long
Period
Long
Short
Jitter
AbsPer Term AVG Term AVG Nominal Term AVG Term AVG AbsPer
Min
Min
Min
Max
Max
Max
99.75
9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107
ns
133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830
ns
Table 10. Absolute Maximum Ratings
Parameter
3.3 V Core Supply Voltage¹
3.3 V Input High Voltage^1,2
3.3 V Input Low Voltage¹
Storage Temperature¹
Input ESD protection³
Symbol
VDD/VDD_A
VIH
VIL
t_s
ESD
Min
—
—
–0.5
–65
2000
Max
4.6
V_DD+0.5 V
—
150
—
Notes:
1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters.
2. Maximum VIH is not to exceed maximum V_DD.
3. Human body model.
Unit
V
V
V
°C
V
12
Rev. 1.3