SI53019-A01A Datasheet, PDF (1/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53019-A01A
19-OUTPUT PCIE GEN 3 BUFFER
Features
 Nineteen 0.7 V current-mode,  Spread spectrum tolerable
HCSL PCIe Gen 3 outputs
 50 ps output-to-output skew
 100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
 Fixed 0 ps input to output delay
 Low phase jitter (Intel QPI, PCIe
Gen 1/Gen 2/Gen 3/Gen 4
 PLL bandwidth SW SMBUS
common clock compliant


programming overrides the latch
value from HW pin
9 selectable SMBus addresses
Fixed external feedback path



Gen 3 SRNS Compliant
100 ps input-to-output delay
Extended Temperature:
–40 to 85 °C
 8 dedicated OE pin
 PLL or bypass mode
 Package: 72-pin QFN
Ordering Information:
See page 32.
Applications
 Server
 Storage
 Data Center
 Network Security
Description
The Si53019-A01A is a 19-output, current mode HCSL differential clock
buffer that meets all of the performance requirements of the Intel
DB1900Z specification. The device is optimized for distributing reference
clocks for Intel^® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/
Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel
SMI) applications. The VCO of the device is optimized to support
100 MHz and 133 MHz operation. Each differential output can be enabled
through I²C for maximum flexibility and power savings. Measuring PCIe
clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool.
Download it for free at www.silabs.com/pcie-learningcenter.
Pin Assignments
VDDA 1
GNDA 2
IREF 3
100M_133M 4
HBW_BYPASS_LBW 5
PWRGD / PWRDN 6
GND 7
VDDR 8
CLK_IN 9
CLK_IN 10
SA_0 11
SDA 12
SCL 13
SA_1 14
FB_IN 15
FB_IN 16
FB_OUT 17
FB_OUT 18
Si53019-A01A
54 OE11
53 DIF_11
52 DIF_11
51 OE10
50 DIF_10
49 DIF_10
48 OE9
47 DIF_9
46 DIF_9
45 VDD
44 GND
43 OE8
42 DIF_8
41 DIF_8
40 OE7
39 DIF_7
38 DIF_7
37 OE6
Patents pending
Rev. 1.3 1/16
Copyright © 2016 by Silicon Laboratories
Si53019-A01A