SI53019-A01A Datasheet, PDF (23/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53019-A01A
4.3. Control Registers
Table 22. Byte 0: PLL Mode and Frequency Select Register
Bit Pin #
Name
Control Function
0
4
100M_133M#
Frequency Select
Readback
1
reserved
2
reserved
3 67/66 Output Enable DIF 16
Output control,
overrides OE# pin
4 70/69 Output Enable DIF 17
Output control,
overrides OE# pin
5 72/71 Output Enable DIF 18
Output control,
overrides OE# pin
6
5
PLL Mode 0
PLL operating mode
readback 0
7
5
PLL Mode1
PLL operating mode
readback 1
0
133 MHz
1
100 MHz
See PLL operating
mode readback table
Type
R
R
R
Default
Latch
0
0
1
1
1
Latch
Latch
Bit Pin #
0 19/20
1 22/23
2 24/25
3 27/28
4 29/30
5 32/33
6 35/36
7 39/38
Table 23. Byte 1: Output Enable Control Register
Description
Output Enable DIF 0
Output Enable DIF 1
Output Enable DIF 2
Output Enable DIF 3
Output Enable DIF 4
Output Enable DIF 5
Output Enable DIF 6
Output Enable DIF 7
Output control,
overrides OE# pin
Output control,
overrides OE# pin
Output control,
overrides OE# pin
Output control,
overrides OE# pin
Output control,
overrides OE# pin
Output control,
overrides OE# pin
Output control,
overrides OE# pin
Output control,
overrides OE# pin
If Bit = 0
Hi-Z
If Bit = 1
Enabled
Type
RW
Default
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Rev. 1.3
23