AN921 Datasheet, PDF (5/24 Pages) Silicon Laboratories – Configurable Logic Unit

AN921: Configurable Logic Unit
D Latch
3. D Latch
Configurable Logic Units can be used to build a D latch. This section shows how this memory circuit can be built without using the D
flip-flop portion of the CLU. This is advantageous in applications where we may want the output of the latch to be sent to another CLU
via the carry input.
3.1 Background
The truth table for a D latch is shown below. When the clock input (CLK) is not rising, the next output (Q_NEXT) will remain the same as
the current output (Q). When the clock is rising and D input is 0, the next output is 0. When the clock is rising and the D input is 1, the
next output is 1.
Table 3.1. Truth Table of D Latch (Simplified)
CLK
D
Q
Q_NEXT
Comments
Non-rising
X
X
Q
Hold state
Rising
0
X
0
Clock rising, D = 0
Rising
1
X
1
Clock rising, D = 1
3.2 D Latch Implementation
To implement the D latch, signals D, CLK and Q must be assigned to CLU inputs and outputs. CLK can be assigned to CLU3's MXA
input. The current output Q can be assigned to CLU3's MXB input. The last available input to CLU3 is the Carry, which always the
output of the previous CLU. Therefore, RESET is assigned to CLU2's MXA, and the CLU2 LUT implements a buffer, as shown below.
CLU2
D ^MXA
CARRY IN
CLU3
CLK ^MXA
Q
MXB
Figure 3.1. Block Diagram of D Latch
The D latch truth table can now be expanded as shown below. When the rows are ordered as shown, the Q_NEXT column read from top
to bottom is the binary value, from most-significant bit to least-significant bit, written to the LUT register to implement the SR latch.
Therefore, CLU1FN should be initialized to 0xAC.
Table 3.2. Truth Table of D Latch (Expanded)
CLK (MXA)
1
1
1
1
0
0
0
0
Q (MXB)
1
1
0
0
1
1
0
0
D (CARRY IN)
1
0
1
0
1
0
1
0
Q_NEXT
1
0
1
0
1
1
0
0
Comments
Clock rising, D = 1
Clock rising, D = 0
Clock rising, D = 1
Clock rising, D = 0
Hold state
Hold state
Hold state
Hold state
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