AN921 Datasheet, PDF (15/24 Pages) Silicon Laboratories – Configurable Logic Unit

6. Biphase Mark Encoder/Decoder
AN921: Configurable Logic Unit
Biphase Mark Encoder/Decoder
6.1 Background
Biphase Mark Code (BMC) combines both data and clock in a single signal. One clock cycle is a BMC bit period. A transition always
occurs at the beginning of each bit period. A logic 1 is represented by a transition (rising or falling edge) in the middle of the bit period.
A logic 0 is represented by no transition in the middle of the period. An example is shown below:
Clock
Data
BMC
0
1
0
0
1
1
0
1
0
0
1
0
Figure 6.1. Biphase Mark Encoded Data
A BMC encoder accepts a data signal and clock signal as inputs and produces a single BMC encoded output. A BMC decoder accepts
a BMC-encoded signal as the input and produces two outputs: data and clock.
BMC is used in standards such as the USB 3.1 Power Delivery Specification CC signaling, AES3 digital audio, or S/PDIF audio.
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