AN921 Datasheet, PDF (21/24 Pages) Silicon Laboratories – Configurable Logic Unit

AN921: Configurable Logic Unit
Biphase Mark Encoder/Decoder
6.3.1 Biphase Mark Decoder Implementation
The implementation of the Biphase Mark decoder will decode a single BMC-encoded signal into separate clock and data signals, which
can be fed into the SPI module for reception. The SPI module allows its SCK slave clock and MOSI input to be taken from CLU outputs.
In this implementation, we also demonstrate how to resynchronize the clock at every bit transition that occurs at the end of every bit.
The block diagram of the decoder logic is shown below:
CLU2
BMC
MXB
T4OVF ^MXA
DQ
CLU3
CARRY IN
PBMC MXA
T4OVF ^ALTCLK
DQ
DATA
(to SPI MOSI)
CLU0
CARRY IN
1
T2OVF ^MXA 0
MXB
Figure 6.6. BMC Decoder Block Diagram
Timer 5
Reload Force
CLU1
MXA
The timing diagram of the BMC encoded signal and the decoded SPI clock and data is shown below:
CLOCK
(to SPI SCK)
A
BMC
PBMC
T4OVF
T2OVF
Timer 2/4 Reload Force
(Run = 0)
CLOCK
DATA
0
1
0
1
E
C
B
D
0
1
0
0.75 TBIT
Figure 6.7. Timing Diagram of BMC Decoder
1
1
The implementation is based on the observation that comparing consecutive samples of the BMC signal at 0.75 bit period away from
the bit boundary can determine the value of the data bit that is transmitted. For example, if the BMC state is 1 at 0.75 bit period away
from the first bit boundary, then it can be determined that the BMC state will be 0 at the second bit boundary. If the BMC is encoded for
DATA = 0 in the second bit period, a transition will not occur at 0.5 bit period after the second bit boundary; hence, the sample at 0.75
bit period after the second bit boundary will still be 0. If the BMC is encoded for DATA = 1 in the second bit period, a transition will occur
at 0.5 bit period after the second bit boundary; hence, the sample at 0.75 bit period after the second bit boundary will be 1. Therefore,
DATA can be implemented by an XNOR Boolean function in CLU3 that takes the current BMC signal and the prior BMC (PBMC) signal
sampled 1 bit period earlier as its inputs.
The Timer 4 overflow is setup to overflow at 0.75 bit period after every bit boundary. The rising edge of the Timer 4 overflow signal will
latch the output of the XNOR result out to the DATA (event B); then, its falling edge 1 SYSCLK cycle later will latch the current logic
level of the current BMC into PBMC via CLU1 (event C). After this clocked PBMC event occurs, the output of the XNOR will be 1 be-
cause the current BMC and the PBMC should be the same logic level. Now, when the Timer 2 overflow occurs another clock cycle later
(event G), it will cause the multiplexer in CLU0 to select the high input, which is the output of the XNOR result. Timers 2 and 4 have
both selected the output of CLU0 to be the force reload signal. As the force reload is now high, this causes Timer 4 and Timer 2 to enter
a reload state to continously reload the 0.75 bit period and 0.75 bit period + 2 sytem clocks respectively into the respective Timer regis-
ters, effectively stopping both counters.
The inputs of the XNOR are the BMC and the latched PBMC of the current bit period. When the current bit period is over, there is a
guaranteed transition in the BMC (event E). This will cause the XNOR output to change to 0, which will cause the CLU0 carry in to
transition to logic 0, forcing the selection to the Timer 2 overflow signal, which is also at logic 0. As the output of CLU0 is now 0, Timers
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