AN921 Datasheet, PDF (18/24 Pages) Silicon Laboratories – Configurable Logic Unit

AN921: Configurable Logic Unit
Biphase Mark Encoder/Decoder
The timing diagram for the case where last BMC transition is a rising edge is shown below. If the last data bit results in a BMC rising
edge, the termination event is delayed to the next bit (event F). As long as the user ensures the subsequent MISO bit is a zero bit, the
final falling edge transition will be generated.
A
B
T2OVF
C
D
MISO
F
T4OVF
SCK
/TXMASK
BMC
0
0
1
0 (IDLE)
Figure 6.4. Timing Diagram of BMC Encoder - Last BMC Transition is a Rising Edge
Timer 2 is setup to overflow at 600 kHz to generate the 300 kbps SCK clock. Timer 4 is initialized to use SYSCLK/12 as its clock, and
its timer is initialized to overflow after the required number of bits are sampled:
TMR4 = -(((uint32_t)(NUM_BITS * 2) * (uint16_t)(-TMR2RL) – 1) / 12);
TMR4RL = -((((uint32_t)(NUM_BITS * 2 + 2) * (uint16_t)(-TMR2RL) – 1) / 12 + TMR4);
The Timer 4 reload register is then set to a value such that it will overflow again one SPI clock later, after accounting for the rounding
effects of the divide-by-12. The second overflow event, if it occurs, ensures that the last transition is always a falling edge. Timer 4 will
be blocked from counting further because the CLU2 output has been assigned to the reload force select (RLFSEL) of the Timer. When
a successful falling transition can be generated (when BMC is sampled high), Timer 4 will stop counting.
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