AN921 Datasheet, PDF (11/24 Pages) Silicon Laboratories – Configurable Logic Unit

AN921: Configurable Logic Unit
Manchester Encoder/Decoder
5.2 Manchester Encoder
In this section, we will demonstrate how to use the CLUs and SPI to combine SPI data and clock signals into a single Manchester-
encoded signal with little CPU intervention.
5.2.1 Manchester Encoder Implementation
The implementation of the Manchester encoder will encode the SPI output into a Manchester-encoded signal. The SPI module signals
for SCK and MOSI are sent to the GPIOs via the priority crossbar decoder, and the CLUs will take these 2 pins as inputs to encode into
Manchester code. The block diagram of the encoder logic is shown below:
CLU0
MOSI
Priority ^MOSI
MXB
SPI _SCK
Crossbar
Decoder
SCK
MXA
DQ
CLU1
X1
MXB
MXA
SYSCLK
DQ
Manchester
Figure 5.2. Manchester Encoder Block Diagram
The timing diagram of the Manchester encoded signal and the original SPI clock and MOSI data are shown below:
SYSCLK
SCK
MOSI
X1
Manchester
B
A
1
0
Figure 5.3. Timing Diagram of Manchester Encoder
The implementation is based on SPI configured with low idle state (CKPOL = 0) and data centered on the first edge (CKPHA = 0), the
rising edge in the implementation. The implementation generates a Manchester code where the bit boundary is aligned with the rising
edge of SCK delayed by a half SYSCLK cycle.
In the implementation, CLU0 is used to generate a data bit representation of MOSI that is valid between the rising edges of SCK (X1,
event A). X1 is then XORed with the SCK in CLU0 to generate the Manchester coded signal. If the LUT output of CLU0 was used for
the Manchester code, there would be glitches because the inputs of the XOR gate, SCK, and X1 transition on the same edge. Hence,
this output is clocked by the inverted SYSCLK to avoid glitches. Due to the synchronous design of the SPI block, we know that the
rising edge of SCK will be aligned to the rising edge of SYSCLK. Hence, we can avoid glitches by using the falling edge of SYSCLK to
clock the XOR output (event B).
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