AN921 Datasheet, PDF (4/24 Pages) Silicon Laboratories – Configurable Logic Unit

AN921: Configurable Logic Unit
SR Latch
2.2 SR Latch Implementation
To implement the SR latch, signals SET, RESET and Q must be assigned to CLU inputs and outputs. SET can be assigned to CLU1's
MXA input. The current output Q can be assigned to CLU1's MXB input. The last available input to CLU1 is the Carry, which always the
output of the previous CLU. Therefore, RESET is assigned to CLU0's MXA, and the CLU0 LUT implements a buffer, as shown below.
RESET
CLU0
MXA
CARRY IN
SET ^MXA
CLU1
MXB
1
Q
0
Figure 2.1. Block Diagram of SR Latch
The SR latch truth table can now be expanded as shown below. When the rows are ordered as shown, the Q_NEXT column read from top
to bottom is the binary value, from most-significant bit to least-significant bit, written to the LUT register to implement the SR latch.
Therefore, CLU1FN should be initialized to 0x74.
Table 2.2. Truth Table of SR Latch (Expanded)
SET (MXA)
1
1
1
1
0
0
0
0
Q (MXB)
1
1
0
0
1
1
0
0
RESET (CARRY IN)
1
0
1
0
1
0
1
0
Q_NEXT
0
1
1
1
0
1
0
0
Comments
*User defined
Set
*User defined
Set
Reset
Hold state
Reset
Hold state
Note: The CLU output cannot be undefined and must be either high or low. Therefore, when SET = RESET = 1, Q_NEXT has been arbi-
trarily defined. Alternatively, CLU1FN could be set to 0xF4, 0xD4 or 0x54.
2.3 Firmware Example
The SR latch firmware example can be found in Simplicity Studio under [Software Examples]>[Kit: EFM8LB1/EFM8BB3 Starter
Kit]>[Configurable Logic]>[Latches]. The example uses CLU0 and CLU1 to implement the previously-discussed configuration for the
SR latch.
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