AN921 Datasheet, PDF (22/24 Pages) Silicon Laboratories – Configurable Logic Unit

AN921: Configurable Logic Unit
Biphase Mark Encoder/Decoder
2 and 4 will restart counting with the reloaded values. This mechanism effectively causes re-synchronization at every bit boundary. This
is desirable because it means that the clocks at both transmit and receive devices need not be exactly the same as the other clock.
Meanwhile, the Timer reload force signal from the output of CLU0 is inverted by CLU1, and the output of CLU1 is the CLOCK with the
rising edge as the clocking edge. The CLOCK signal is also used for the Timer 5 reload force, where Timer 5 is used to detect if the
BMC line has gone idle. If a Timer 5 overflow event occurs, it means that the BMC signal is inactive and no data is arriving. This is
illustrated in the timing diagram below.
BMC
PBMC
T4OVF
T2OVF
Timer 2/4 Reload Force
(Run = 0)
CLOCK
DATA
0
A
0
IDLE
C
B
D
0
0
IDLE
Figure 6.8. Timing Diagram of BMC Going Idle
The reason for setting the SPI clock to stay low idle is because there are no more BMC transitions when the line is idle. This means that
the falling edge event on Timer 2/4 reload force (event E in Figure 6.7 Timing Diagram of BMC Decoder on page 20) will not occur. This
effectively stops Timers 2 and 4 while allowing Timer 5 to eventually overflow because the SPI clock will no longer return to high to
force reload Timer 5.
The SPI SCK and MOSI inputs are connected directly to the CLU outputs CLOCK and DATA respectly. CLOCK and DATA are not
routed to GPIO pins to conserve GPIO usage.
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