AN921 Datasheet, PDF (17/24 Pages) Silicon Laboratories – Configurable Logic Unit

AN921: Configurable Logic Unit
Biphase Mark Encoder/Decoder
6.2.1 Biphase Mark Encoder Implementation
This implementation also demonstrates how to transmit only a non-divisible-by-8 number of bits using a Timer and CLU without CPU
intervention. The block diagram of the encoder logic is shown below:
CLU2
MXB
T4OVF ^MXA
DQ
SPI
MISO
Priority
Crossbar
Decoder
CLU1
MXA
T2OVF ^ALTCLK
DQ
/TXMASK
CLU3
CARRY IN
1
MISO MXA
0
SCK MXB
MXB
CARRY IN
T2OVF ^MXA
CLU0
DQ
BMC
Figure 6.2. BMC Encoder Block Diagram
The design ensures that the last BMC transition is a falling edge. The timing diagram of the BMC encoded signal and the MISO data
are shown below:
A
B
T2OVF
C
D
MISO
E
T4OVF
SCK
/TXMASK
BMC
1
0
1
0 (IDLE)
Figure 6.3. Timing Diagram of BMC Encoder - Last BMC Transition is a Falling Edge
CLU1 generates the SPI slave clock, and the MISO output is sent to the CLU3 via the priority crossbar. The SPI is configured with low
idle state (CKPOL = 0) and data centered on the second edge (CKPHA = 1), the falling edge. The rising edge of SCK corresponds the
BMC bit boundary (event A and event B in the Timing Diagram). A BMC signal always has a transition at every bit boundary (event C).
This is achieved via CLU3 selecting the inverse of the original BMC output. When the falling edge of SCK occurs, CLU3 selects the
XOR of the MISO and the current BMC output; this inverts the BMC output if the MISO bit is 1. When the next falling edge of Timer 2
overflow occurs in the middle of the bit period, this is clocked into the BMC output (event D).
The CLU2 output generates the mask used to force the BMC output to low (event E). This design ensures that BMC transmission, with
a non-divisible-by 8 number of bits, stops automatically without CPU intervention. Firmware detects the end of transmission by sensing
for the CLU2 output rising edge. CLU0 clocks in the BMC output one clock cycle later because it uses the inverted Timer 2 overflow,
which is also used to generate the SPI SCK slave clock. The rising edge of the Timer 2 overflow clocks the transitions of many signals,
so the inverted clock is used in CLU0 to prevent glitches in the BMC output.
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