AN921 Datasheet, PDF (13/24 Pages) Silicon Laboratories – Configurable Logic Unit

AN921: Configurable Logic Unit
Manchester Encoder/Decoder
5.3 Manchester Decoder
In this section, we will demonstrate how to use the CLUs, Timers and SPI can be used to decode Manchester data with little CPU inter-
vention.
5.3.1 Manchester Decoder Implementation
The implementation of the Manchester decoder will decode the single-wire signal into its clock and data, which can be fed into the SPI
module. The SPI module allows its SCK slave clock and MOSI input to be taken from CLU outputs. In this implementation, the clock is
re-synchronized at the end of every bit period. The block diagram of the decoder logic is shown below:
CLU2
CLU3
CARRY IN
DATA
CARRY IN
CLU0
Manchester MXB
Code
DQ
Latched MC
CLU1
MXA
T2OVF
DQ
MXB
CLOCK MXA
Figure 5.5. Manchester Decoder Block Diagram
The timing diagram of the Manchester encoded signal and the decoded SPI clock and data are shown below:
Timer 2
Reload Force
1
0
0
1
1
0
A
MC/DATA
B
Latched MC
Timer 2 Reload Force
(Run = 0)
CLOCK
Figure 5.6. Timing Diagram of Manchester Decoder
The implementation is based on the observation that the data bit can be sampled in the second half of the Manchester code. A Man-
chester code always contains a transition in the middle of the bit period, which can be used to start a timer to generate the sampling
edge. The Manchester code itself can be used as the DATA signal as long as we generate an SCK where the clocking edge is some-
where in the second half of the Manchester bit. In the figure above, CLU2 provides the DATA signal. The LUT logic merely passes the
Manchester signal through.
Timer 2 is set to reload every 0.375 bit period. Its reload force select signal is configured to use the CLU0 output. CLU0 is designed
such that when a mid-bit transition occurs (event A), its output will go low, starting Timer 2. After the first Timer 2 overflow, CLU1 gener-
ates the rising edge of SCK, sampling the Manchester signal. When CLOCK is high, it forces the Timer 2 reload force signal to remain
low. When the second Timer 2 overflow occurs, CLU1 generates the falling edge of CLOCK. The falling edge of CLOCK causes two
events: CLU2 will sample the MOSI input, and Timer 2 reload force signal will go high, resetting Timer 2 and freezing it until the next
mid-bit transition (event B).
The SPI SCK and MOSI inputs are connected directly to the CLU outputs CLOCK and DATA respectly. CLOCK and DATA are not
routed to GPIO pins to conserve GPIO usage.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.1 | 12