ISL28023 Datasheet, PDF (48/55 Pages) Intersil Corporation – Bidirectional current sensing

ISL28023
External Clock
VIN = 4.5V TO 36V
VIN
SMBALERT1
VINP
ISL28023
3.3V
Vreg
VCC
GND
VIN
Ext_Temp
Place Diode
Near RSH
Phase
VINM
VBUS
ISL85415
SYNC
Lo
0.1µF
Boot
AUXP
AUXM
AUXV
DAC OUT
PG
En
FB
R1
EXT CLK
To SMBAlert1
VIN
ADC
16-Bit
8-Bit
DAC
PMBus
REG
MAP
Temp
Sense
A0
A1
A2
SCL
SDA
SMBALERT2
I2CVCC
VOUT = 0.6 +
(0.6 – DAC OUT)
* R2/R1
System_Clock
GPIO
GPIO
MCU
GPIO/Int
SCL
SDA
FIGURE 112. SIMPLIFIED SCHEMATIC OF THE ISL28023
SYNCHRONIZED TO A MCU SYSTEM CLOCK
An externally controlled clock allows measurements to be
synchronized to an event that is time dependent. The event could
be application generated, such as timing a current measurement
to a charging capacitor in a switch regulator application or the
event could be environmental. A voltage or current measurement
may be susceptible to crosstalk from a controlled source. Instead
of filtering the environmental noise from the measurement,
another approach would be to synchronize the measurement to
the source. The variability and accuracy of the measurement will
improve.
The ISL28023 has the functionality to allow for synchronization
to an external clock. The speed of the external clock combined
with the choice of the internal chip frequency division value
determines the acquisition times of the ADC. The internal system
clock frequency is 500kHz. The internal system clock is also the
ADC sampling clock. The acquisition times scale linearly from
500kHz. For example, an external clock frequency of 4.0MHz
with a frequency divide setting of 0 (internal divide by 8) results
in acquisition times that equal the internal oscillator frequency
when enabled. The ADC modulator is optimized for frequencies
of 500kHz. Operating internal clock frequencies beyond 500kHz
may result in measurement accuracy errors due to the modulator
not having enough time to settle.
Suppose an external clock frequency of 5.5MHz is applied with a
divide by 88 internal frequency setting, the system clock speed is
62.5kHz or 8x slower than the internal system clock. The
acquisition times for this example will increase by 8. For a
channel’s conversion time setting of 2.048ms, the ISL28023 will
have an acquisition time of 256µs.
FIGURE 113. EXTERNAL CLOCK MODE
Figure 113 illustrates a simple mathematical diagram of the
ECLK pin internal connection. The external clock divide is
controlled by way of the EXTCLKDIV bit in register 0xE5.
0.5
-1.5
-3.5
ExtClkDiv = 3
-5.5
ExtClkDiv = 4
-7.5
ExtClkDiv = 14
-9.5
ExtClkDiv = 0
ExtClkDiv = 1
-11.5
FreqExtClk = 16MHz
-13.5 ADC TIME SETTING
(Config_Ichannel) = 0
-15.510
100
1k
10k
FREQUENCY (Hz)
100k
FIGURE 114. MEASUREMENT BANDWIDTH vs EXTERNAL CLK
FREQUENCY
Figure 114 illustrates how changing the system clock frequency
effects the measurement bandwidth (the ADC acquisition time).
The bandwidth of the external clock circuitry is 25MHz.
Figure 115 shows the bandwidth of the external clock circuitry
when the external clock division bits equals to 0.
0.5
-0.5
-1.5
-2.5
-3.5
-4.5
-5.5
-6.5
ExtDiv = 0; (Freq_Int = Freq_ExtClk/8)
-7.5
-8.5
0.01
0.1
1
10
100
ExtClk FREQUENCY (MHz)
FIGURE 115. EXTERNAL CLOCK BANDWIDTH vs MEASUREMENT
ACCURACY
Submit Document Feedback ₄₈
FN8389.5
March 18, 2016