ISL28023 Datasheet, PDF (32/55 Pages) Intersil Corporation – Bidirectional current sensing

ISL28023
Global IC Controls
0X12 RESET DEFAULT ALL (S)
The Restore Default All register is a send byte command that
restores all registers to the default state defined in Table 2.
0X01 OPERATION (R/W)
The Operation register is a read/writable byte register that
controls the overall power up state of the chip. Data Bit 7 of the
register configures the power status of the chip. The power status
is defined in Table 7. Yellow shading in the table is the default
setting of the bit at power-up.
TABLE 7. 0x01 OPERATION REGISTER BIT7 DEFINED
D7
STATUS
0
Power-Down
1
Normal Operation
Primary and Auxiliary Channel Controls
0XD2 SET DPM MODE (R/W)
The Set DPM Mode is a read/writable byte register that controls
the data acquisition behavior of the chip.
TABLE 8. 0xD2 SET DPM MODE REGISTER DEFINITION
BIT
NUMBER D[7] D6
D[5] D[4] D[3] D[2:0]
Bit Name N/A ADC
Enable
ADC
State
Post
Trigger
State
ADC Operating
Mode Mode
Type
Default Value 0
0
0
0
1
010
ADC ENABLE D[6]
Data Bit 6 of the Set DPM Mode register controls the ADC power
state within the DPM chip. At power-up, the ADC is powered up
and is available to take data.
TABLE 9. 0xD2 SET DPM MODE REGISTER BIT6 DEFINED
D6
ADC PD
0
Normal Mode
1
ADC Powered Down
ADC STATE D[5]
Data Bit5 of the Set DPM Mode register controls the ADC state.
The idle state of the ADC does not acquire data from any input of
the DPM. Normal operating mode has the ADC acquiring data in
a systematic way.
TABLE 10. 0xD2 SET DPM MODE REGISTER BIT5 DEFINED
D5
ADC STATE
0
Normal State
1
ADC in Idle State
POST TRIGGER STATE D[4]
Data Bit 4 of the Set DPM Mode register controls the post ADC
state once an acquisition has been made in the trigger mode.
TABLE 11. 0xD2 SET DPM MODE REGISTER BIT4 DEFINED
D4
POST TRIGGER STATE
0
Idle Mode after a Trigger Measurement
1
PD Mode after Trigger Measurement
ADC MODE TYPE D[3]
Data Bit 3 of the Set DPM Mode register controls the behavior of
the ADC to either triggered or continuous. The continuous mode
has the ADC continuously acquiring DAT in a systematic manor
described by data Bits[2:0] in the set DPM mode register. The
triggered mode instructs the ADC to make an acquisition
described by data Bits[2:0]. The beginning of a triggered cycle
starts once writing to the Set DPM Mode register commences.
The trigger mode is useful for reading a single measurement per
acquisition cycle.
TABLE 12. 0xD2 SET DPM MODE REGISTER BIT3 DEFINED
D3
ADC MODE TYPE
0
Trigger
1
Continuous
OPERATING MODE D[2:0]
The Operating Mode bits of the Set DPM Mode register controls the
state machine within the chip. The state machine globally controls
the overall functionality of the chip. Table 13 shows the various
measurement states the chip can be configured to, as well as the
mode bit definitions to achieve a desired measurement state. The
shaded row is the default setting upon power-up.
TABLE 13. 0xD2 SET DPM MODE REGISTER BITS 2 TO 0 DEFINED
D[2:0]
MEASUREMENT INPUT
0
Primary Channel Shunt Voltage
1
Primary Channel V_BUS Voltage
2
Primary Shunt and V_BUS Voltages
3
Auxiliary Channel Shunt Voltage
4
Auxiliary Channel V_BUS Voltage
5
Auxiliary Shunt and V_BUS Voltages
6
Internal Temperature
7
All
0XD3 DPM CONVERSION STATUS (R)
The DPM Conversion Status register is a readable byte register
that reports the status of a conversion when the DPM is
programmed in the trigger mode.
TABLE 14. 0xD3 DPM CONVERSION STATUS REGISTER DEFINITION
BIT NUMBER
D[7:2]
D[1]
D[0]
Bit Name
N/A
CNVR
OVF
Default Value
0
0
0
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FN8389.5
March 18, 2016