ISL28023 Datasheet, PDF (45/55 Pages) Intersil Corporation – Bidirectional current sensing

ISL28023
Device Addressing
Following a start condition, the master must output a slave
address byte. The 7 MSBs are the device identifiers. The A0, A1
and A2 pins control the bus address (these bits are shown in
Table 49). There are 55 possible combinations depending on the
A0, A1 and A2 connections.
The last bit of the slave address byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 102).
After loading the entire slave address byte from the SDA bus, the
device compares with the internal slave address. Upon a correct
compare, the device outputs an acknowledge on the SDA line.
A2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I2CVCC
...............
I2CVCC
SDA
SDA
...............
SDA
SCL
...............
SCL
SCL
TABLE 49. I²C SLAVE ADDRESSES
A1
A0
GND
GND
GND
I2CVCC
GND
SDA
GND
SCL
I2CVCC
GND
I2CVCC
I2CVCC
I2CVCC
SDA
I2CVCC
SCL
SDA
GND
SDA
I2CVCC
SDA
SDA
SDA
SCL
SCL
GND
SCL
I2CVCC
SCL
SDA
SCL
SCL
GND
GND
..............
..............
SCL
SCL
GND
GND
GND
VCC
..............
..............
SCL
SCL
GND
GND
..............
..............
SDA
X
SCL
X
SLAVE ADDRESS
1000 000
1000 001
1000 010
1000 011
1000 100
1000 101
1000 110
1000 111
1001 000
1001 001
1001 010
1001 011
1001 100
1001 101
1001 110
1001 111
1010 000
..................
1011 111
1100 000
Do Not Use. Reserved
..................
1101 111
1110 000
..................
Do Not Use. Reserved
Do Not Use. Reserved
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FN8389.5
March 18, 2016