ISL28023 Datasheet, PDF (46/55 Pages) Intersil Corporation – Bidirectional current sensing

ISL28023
Following the slave byte is a one byte word address. The word
address is either supplied by the master device or obtained from
an internal counter. On power-up, the internal address counter is
set to address 00h, so a current address read starts at address
00h. When required, as part of a random read, the master must
supply the one word address bytes, as shown in Figure 108.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the registers, the slave byte must be “1nnnnnnx”
in both places.
Write Operation
A write operation requires a START condition, followed by a valid
identification byte, a valid Address byte, two data bytes and a
STOP condition. The first data byte contains the MSB of the data,
the second contains the LSB. After each of the four bytes, the
device responds with an ACK. At this time, the I²C interface
enters a standby state.
Read Operation
A read operation consists of a three byte instruction, followed by
two data bytes (see Figure 108). The master initiates the operation
issuing the following sequence: A START, the identification byte
with the R/W bit set to “0”, an address byte, a second START and a
second identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL28023 responds with an ACK. Then the
ISL28023 transmits two data bytes as long as the master
responds with an ACK during the SCL cycle following the eighth bit
of the first byte. The master terminates the read operation (issuing
no ACK then a STOP condition) following the last bit of the second
data byte (see Figure 108).
The data bytes are from the memory location indicated by an
internal pointer. This pointer’s initial value is determined by the
address byte in the read operation instruction and increments by
one during transmission of each pair of data bytes.
SLAVE ADDRESS
1
n
n
n
n
n
n R/W _BYTE
A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS
D15 D14 D13 D12 D11 D10 D9 D8 DATA BYTE 1
D7 D6 D5 D4 D3 D2 D1 D0 ^{DATA BYTE 2}
FIGURE 107. SLAVE ADDRESS, WORD ADDRESS AND DATA BYTES
Group Command
The DPM has a feature that allows the master to configure the
settings of all DPM chips at once. The configuration command for
each device does not have to be same. Device 1 on an I²C bus could
be configured to set the voltage threshold of the OV comparator
while device 2 is configured for the acquisition time of the V_BUS
input. To achieve the scenario described without group command,
the master sends two write commands, one to each slave device.
Each command sent from the master has a start bit and a stop bit.
The group command protocol concatenates the two commands but
replaces the stop bit of the first command and the start bit of the
second command with a repeat start bit. The actions sent in a Group
Command format will execute once the stop bit has been sent. The
stop bit signifies the end of a packet.
The broadcast feature saves time in configuring the DPM as well
as measuring signal parameters in time synchronization. The
broadcast should not be used for DPM read backs. This will
cause all devices connected to the I²C bus to talk to the master
simultaneously.
SIGNALS
FROM THE
MASTER
S
T _{IDENTIFICATION}
A
R
T
BYTE WITH
R/W = 0
ADDRESS
BYTE
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 1
S
A
T
C
O
K
P
SIGNAL AT
SDA
1nnnnnn0
A
SIGNALS FROM
C
THE SLAVE
K
1nnnnnn1
A
A
C
K
C
K
FIRST READ
DATA BYTE
FIGURE 108. READ SEQUENCE (SLAVE ADDRESS SHOWN AS nnnnnn)
SIGNALS
S
FROM THE
T
MASTER ^A
R
T
MASTER
CODE
S
T ^{SLAVE ADDRESS}
ADDRESS
A ^{IDENTIFICATION}
BYTE
R
T
BYTE _WRITE/READ
DATA
BYTE
SECOND READ
DATA BYTE
DATA
BYTE
TERMINATES HS
MODE
S
T
O
P
SIGNAL AT
SDA
00001xxx
1nnnnnnx
SIGNALS TO THE
ISL28023
N
fclk ≤ 400kHz
A
C
K
A
A
A
N
C
C
C
A
K
K
K
C
K
fclk UP TO 3.4MHz
FIGURE 109. BYTE TRANSACTION SEQUENCE FOR INITIATING DATA RATES ABOVE 400kbs
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FN8389.5
March 18, 2016