ISL28023 Datasheet, PDF (31/55 Pages) Intersil Corporation – Bidirectional current sensing

ISL28023
IC Device Details
0X19 CAPABILITY (R)
The capability register is a read only byte register that describes
the supporting communication standard by the DPM chip.
TABLE 3. 0x19 CAPABILITY REGISTER DEFINITION
BIT
NUMBER D7
D[6:5]
D4
D[3:0]
Bit Name PEC Max Bus Speed SMB Alert
N/A
Support
Default
1
01
Value
1
0000
The DPM chip supports Packet Error Correction (PEC) protocol.
The maximum PMBus bus speed that the DPM supports is
400kHz. The DPM supports a higher speed option that is not
compliant to the PMBus standard. The higher speed option is
discussed later in the datasheet. The DPM chip has SMB alert
pins which, supports SMB alert commands.
0X20 V_OUT MODE (R)
The V_OUT Mode register is a readable byte register that describes
the method to calculate read back values from the DPM such as
voltage, current, power and temperature. The value for the
register is 0x40. The register value represents a direct data read
back format. For unsigned registers such as V_BUS, the register
value is calculated using Equation 1.
 ^{Register Value}
 ¹⁵




Bit_Val_n2^{n}


^{n  0}

(EQ. 1)
Otherwise, Equation 2 is used for signed readings.
 ^{Register Value}
 ¹⁴




Bit_Val_n2^{n}





Bit_Val₁₅2^{15}
^{n  0}

(EQ. 2)
n is the bit position within the register value. Bit_Val is the value
of the bit either 1 or 0.
0X99 PMBUS REV (R)
The PMBUS Rev register is a readable byte register that describes
the PMBUS revision that the DPM is compliant to.
TABLE 4. 0x99 PMBUS REV REGISTER DEFINITION
BIT NUMBER
D[7:4]
D[3:0]
Bit Name
PMBUS Rev Part I
PMBUS Rev Part II
Default Value
0010
0010
PMBUS Rev part 1 is a PMBus specification pertaining to
electrical transactions and hardware interface. PMBUS Rev
part 2 specification pertains to the command calls used to
address the DPM.
A nibble of 0000 translates to revision 1.0 of either PMBUS
revision. A nibble of 0001 equals 1.1 of either PMBUS revision.
0XAD IC DEVICE ID (BR)
The IC Device ID is a block readable register that reports the
device product name being addressed. The product ID that is
stored in the register is “ISL28023”. Each character is stored as
an ASCII number. A 0x30 equals ASCII “0”. A 0x49 translates to
an ASCII “I”. Figure 97 illustrates the convention for performing a
block read.
0XAE IC_DEVICE_REV (BR)
The IC Device Revision is a block readable register that reports
back the revision number of the silicon and the version of the
silicon. The register is 3 bytes in length.
TABLE 5. 0xAE IC DEVICE REV REGISTER DEFINITION
BIT NUMBER
D[23:12]
D[11]
D[10:0]
Bit Name
N/A
Silicon Version Silicon Revision
Default Value 0000 0011 0000
1
000 0000 0010
SILICON VERSION D[11]
Data Bit11 of the IC Revision register reports the version of the
silicon.
TABLE 6. D[11] SILICON VERSION BIT DEFINED
D16
STATUS
0
60V
1
12V
FIGURE 97. BLOCK READ SMBUS PROTOCOLS WITH AND WITHOUT PEC. DIAGRAMS COPIED FROM SMBUS SPECIFICATION DOCUMENT. THE
DOCUMENT CAN BE UPLOADED AT http://smbus.org/specs/
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FN8389.5
March 18, 2016