ISL28023 Datasheet, PDF (43/55 Pages) Intersil Corporation – Bidirectional current sensing

ISL28023
FIGURE 103. SIMPLIFIED BLOCK DIAGRAM OF THE MARGIN DAC
FUNCTIONS WITHIN THE DPM
The voltage margining feature can be used to improve accuracy
of the voltage applied to the load of a system. For nonfeedback
driving applications, the sense resistor used to measure current
to the load reduces the voltage to the load. The voltage drop from
the sense resistor can be a large percentage with respect to the
supply voltage for point of load applications.
0XE4 CONFIGURE VOL MARGIN (R/W)
The Configure VOL Margin register is a read/writable byte
register that controls the functionality of the voltage margin DAC.
TABLE 46. 0xE4 CONFIGURE VOL MARGIN REGISTER DEFINITION
BIT NUMBER D[7:6] D[5:3] D[2]
D[1]
D[0]
Bit Name
N/A MDAC_HS Load DAC_OEN DAC_EN
Default
00
00 0
0
0
0
Value
MDAC_HS D[5:3]
The MDAC_HS bits control the half-scale output voltage from the
margin DAC. There are 8 half-scale voltages the margin DAC can
be programmed to. Table 47 lists the selections.
TABLE 47. MDAC_HS BITS DEFINED
MDAC_HS[2:0]
HALF-SCALE VOLTAGE (V)
000
0.4
001
0.5
010
0.6
011
0.7
100
0.8
101
0.9
110
1.0
111
1.2
The voltage at the DAC_OUT is the value of the MDAC_HS setting
when the Set VOL Margin register equals 0x80.
LOAD D[2]
The Load bit programs the Set VOL Margin register to the DAC.
The DAC is programmed when the Load bit is programmed from
a 0 to a 1.
DAC_OEN D[1]
The DAC_OEN bit either enables or disables the output of the
margin DAC. Setting the bit to a 1 connects the output of the
margin DAC to the DAC_OUT pin.
DAC_EN D[0]
The DAC_EN bit either enables or disables the margin DAC
circuitry. Setting the bit to a 1 powers up the margin DAC making
it operational to use.
0XE3 SET VOL MARGIN (R/W)
The Set VOL Margin register is an unsigned read/writable byte
register that controls the output voltage of the margin DAC
referenced to the half-scale setting.
TABLE 48. 0xE3 SET VOL MARGIN REGISTER DEFINITION
BIT NUMBER
D[7:0]
Bit Name
MDAC[7:0]
Default
Value
0000 0000
The full-scale voltage is twice the half-scale range minus the DAC
LSB for the margin DAC half-scale range. A half-scale setting of
1.0V has a full-scale setting of 1.992V. The LSB for the margin
DAC is a function of the half-scale setting. Using Equation 17, the
LSB for the margin DAC is calculated as;
MDAC_LSB
2MDAC_HS
2⁸
2MDAC_HS
256
(EQ. 17)
MDAC_HS is the half-scale setting for the voltage DAC.
The VOL margin register value for programming the DAC to a
specific voltage is calculated using Equation 18.
MDAC_value
integer



Vout_desired
MDAC_LSB



(EQ. 18)
The value for VOUT_desired ranges from 0V to two times the
MDAC_HS value minus one MDAC_LSB.
SMBus/I²C Serial Interface
The ISL28023 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL28023 operates as a slave device in all
applications.
The ISL28023 uses two bytes data transfer, all reads and writes
are required to use two data bytes. All communication over the
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FN8389.5
March 18, 2016