ISL28023 Datasheet, PDF (37/55 Pages) Intersil Corporation – Bidirectional current sensing

ISL28023
The temperature threshold reference level has one range setting
which equals +125°C at full-scale.
TABLE 23. Vbus_Thres_Rng BITS DEFINED
Vbus_Thres_Rng: D[8:6]
Vbus_12V Vbus_60V
(RANGE) (RANGE)
0
0
0
12
48
0
0
1
6
24
0
1
0
3
12
0
1
1
1.25
5
1
0
0
X
3.3
1
0
1
X
2.5
VBUS_OV_OT_SET D[5:0]
The Vbus_OV_OT_Set bits controls the voltage/temperature level
to the input of the OV comparator. The LSB of the DAC is 1.56%
of the full-scale range chosen using the Vbus_Thres_Rng bits. For
the temperature feature, the LSB for the temperature level is
5.71°C. The mathematical range is -144°C to +221.4°C.
The overvoltage range starts at 25% of the full-scale range
chosen using the Vbus_Thres_Rng bits and ends at 125% of the
chosen full-scale range. The same range applies to the
temperature measurements.
TABLE 24. Vbus_OV_OT_Set BITS DEFINED
Vbus_OV_OT_Set: D[5:0] OV THRESHOLD VALUE OT THRESHOLD VALUE
00 0000
25% of FS
-144
00 0001
(25 + 1.56)% of FS
-138.3
00 0010
(25 + 3.12)% of FS
-132.6
...............
....................
....................
11 1101
(125 to 4.68)% of FS
210
11 1110
(125 to 3.12)% of FS
215.7
11 1111
(125 to 1.56)% of FS
221.4
Table 24 defines an abbreviated breakdown to set the OV/OT
comparator level. The shaded row is the default condition.
0XDB V_OUT UV THRESHOLD SET (R/W)
The V_OUT UV Threshold Set register is a read/writable byte
register that controls the threshold voltage level to the
undervoltage comparator. The description of the functionality
within this register is found in Table 25.
The compared reference voltage level to the UV comparator is
generated from a 6-bit DAC. The 6-bit DAC has 4 to 6 voltage
ranges that are determined by the Vbus_Thres_Rng bits in the
V_OUT OV Threshold Set register.
TABLE 25. 0xDB V_OUT UV THRESHOLD SET REGISTER DEFINITION
BIT NUMBER
D[7:6]
D[5:0]
Bit Name
N/A
Vbus_UV_Set
Default Value
00
00 0000
VBUS_UV_SET D[4:0]
The Vbus_UV_Set bits control the undervoltage level to the input
of the UV comparator. The LSB of the DAC is 1.56% of the
full-scale range chosen using the Vbus_Thres_Rng bits.
The undervoltage ranges from 0% to 100% of the full-scale range
set by the Vbus_Thres_Rng bits.
TABLE 26. Vbus_UV_Set BITS DEFINED
Vbus_UV_Set: D[5:0]
00 0000
00 0001
00 0010
...............
11 1101
11 1110
11 1111
UV THRESHOLD VALUE
0%
1.56% of FS
3.12% of FS
....................
(100 - 4.68)% of FS
(100 - 3.12)% of FS
(100 - 1.56)% of FS
Table 26 defines an abbreviated breakdown to set the
undervoltage comparator levels. The shaded row is the default
condition.
0XDC I_OUT OC THRESHOLD SET (R/W)
The I_OUT OC Threshold Set register is a read/writable word
register that controls the threshold current level to the
overcurrent comparator. The description of the functionality
within this register is found in Table 27.
TABLE 27. 0xDC I_OUT OC THRESHOLD SET REGISTER DEFINITION
BIT
NUMBER D[15:10] D[9] D[8:7] D[6]
D[5:0]
Bit Name N/A Iout_Dir N/A V_SHUNT Vshunt_OC_Set
Thres
Rng
Default 0000 00 0
00
0
Value
11 1111
The overcurrent threshold is defined through the V_SHUNT reading.
The product of the current through the shunt resistor defines the
V_SHUNT voltage to the DPM. The current through the shunt
resistor is directly proportional the V_SHUNT voltage measured by
the DPM. An overvoltage threshold for V_SHUNT is the same as an
overcurrent threshold.
IOUT_ DIR D[9]
The Iout_Dir bit controls the polarity of the V_SHUNT voltage
threshold. The bit functionality allows an overcurrent threshold to
be set for currents flowing from VINP to VINM and the reverse
direction. Table 28 defines the range settings for the V_BUS
threshold detector. The yellow shaded row denotes the default
setting.
TABLE 28. Vbus_Thres_Rng BITS DEFINED
Iout_Dir: D[9]
CURRENT DIRECTION
0
VINP to VINM
1
VINM to VINP
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March 18, 2016