ISL28023 Datasheet, PDF (41/55 Pages) Intersil Corporation – Bidirectional current sensing

ISL28023
TABLE 41. 0x7E STATUS CML REGISTER DEFINITION
BIT NUMBER D[7] D[6]
D[5] D[4:2] D[1] D[0]
Default Value 0
0
0
0 00
0
0
USCMD D[7]
The USCMD bit is set to 1 when an unsupported command is
received from the I²C master. Reading from an undefined
register is an example of an action that would set the USCMD bit.
The USCMD bit is a latched bit. Writing a 1 to the USCMD bit
clears the warning resulting in a bit value equal to 0.
USDATA D[6]
The USDATA bit is set to 1 when an unsupported data is received
from the I²C master. Writing a word to a byte register is an
example of an action that would set the USDATA bit. The USDATA
bit is a latched bit. Writing a 1 to the USDATA bit clears the
warning resulting in a bit value equal to 0.
PECERR D[5]
The PECERR bit is set to 1 when a Packet Error Check (PEC) event
has occurred. Writing the wrong PEC to the DPM is an example of
an action that would set the PECERR bit. The PECERR bit is a
latched bit. Writing a 1 to the PECERR bit clears the warning
resulting in a bit value equal to 0.
COMERR D[1]
The COMERR bit is set to 1 for communication errors that are not
handled by the USCMD, USDATA and PECERR errors. Reading
from a write only register is an example of an action that would
set the COMERR bit. The COMERR bit is a latched bit. Writing a 1
to the COMERR bit clears the warning resulting in a bit value
equal to 0.
0X78 STATUS BYTE (R/W)
The Status Byte register is a read/writable byte register that is a
hierarchal register to the Status Temperature and Status CML
registers. The Status Byte registers bits are set if an over
temperature or a CML error has occurred.
TABLE 42. 0x78 STATUS BYTE REGISTER DEFINITION
BIT NUMBER D[7] D[6:3]
D[2]
D[1]
D[0]
Bit Name BUSY N/A Temperature CML
N/A
Default Value 0
000 0
0
0
0
BUSY D[7]
The BUSY bit is set to 1 when the DPM is busy and unable to
respond. The BUSY bit is a latched bit. Writing a 1 to the BUSY bit
clears the warning resulting in a bit value equal to 0.
TEMPERATURE D[2]
The Temperature bit is set to 1 when an over-temperature fault
occurs from the internal temperature sensor. This bit is the same
action bit as the OT Warning bit in the Status Temperature
register. The over-temperature threshold is set from the V_OUT OV
Threshold Set register. In the event of an over-temperature
condition, the Temperature bit is latched to 1. Writing a 1 to the
Temperature bit will clear the warning resulting in a bit value
equal to 0.
CML D[1]
The CML bit is set to 1 when any errors occur within the Status
CML register. There are four Status CML error bits that can set
the CML bit. The CML bit is a latched bit. Writing a 1 to the CML
bit clears the warning resulting in a bit value equal to 0.
0X79 STATUS WORD (R/W)
The Status Word register is a read/writable word register that is a
hierarchal register to the Status V_OUT, Status I_OUT and Status
Byte registers. The Status Word registers bits are set when any
errors previously described occur. The register generically reports
all errors.
TABLE 43. 0x79 STATUS WORD REGISTER DEFINITION
BIT NUMBER D[15] D[14] D[13:8]
D[7:0]
Bit Name
Default
Value
V_OUT
0
I_OUT
N/A
See Status Byte
0
00 0000
0000 0000
V_OUT D[15]
The V_OUT bit is set to 1 when any errors occur within the Status
V_OUT register. Whether either or both an undervoltage or
overvoltage fault occurs, the V_OUT bit will be set. The V_OUT bit is a
latched bit. Writing a 1 to the V_OUT bit clears the warning
resulting in a bit value equal to 0.
I_OUT D[14]
The I_OUT bit is set to 1 when an overcurrent fault occurs. This bit
is the same action bit as the I_OUT OC Warning bit in the Status
I_OUT register. In the event of an overcurrent condition, the I_OUT bit
is latched to 1. Writing a 1 to the I_OUT bit will clear the warning
resulting in a bit value equal to 0.
0X1B SMBALERT MASK (BR/BW)
0XDF SMBALERT2 MASK (BR/BW)
The SMBALERT registers are block read/writable registers that
mask error conditions from electrically triggering the respective
SMBALERT pin.
The SMBALERT can mask bits of any of the status registers.
Masking lower level bits prevents hierarchal bit from being set.
For example, a COMERR bit being masked will not set the CML
bit of the Status Byte register.
To mask a bit, the first data byte is the register address of the
bit(s) to be masked. The second and third data bytes are the
masking bits of the register. A masking bit of 1 prevents the
signal from triggering an interrupt.
All alert bits are masked as the default state for both the SMB
alert pins. The master needs to send instructions to unmask the
alert bits.
As an example, a user would like to allow the COMERR bit to
trigger a SMBALERT2 interrupt while masking the rest of the
alerts within the Status CML register. The command that is sent
from the master to the DPM is the slave address, SMBALERT2
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FN8389.5
March 18, 2016