ISL28023 Datasheet, PDF (33/55 Pages) Intersil Corporation – Bidirectional current sensing

ISL28023
CNVR: CONVERSION READY D[1]
The Conversion Ready bit indicates when the ADC has finished a
conversion and has transferred the reading(s) to the appropriate
register(s). The CNVR is only operable when the ADC state is set
to trigger. The CNVR is in a low state when the conversion is in
progress. When the CNVR bit transitions from a low state to a
high state and remains at a high state, the conversion is
complete. The CNVR initializes or reinitializes when writing to the
Set DPM Mode register.
OVF: MATH OVERFLOW FLAG D[0]
The Math Overflow Flag (OVF) bit is set to indicate the current and
power data being read from the DPM is overranged and
meaningless.
0XD4 CONFIGURE ICHANNEL (R/W)
The Configure IChannel register is a read/writable word register
that configures the ADC measurement acquisition settings for
the primary and auxiliary voltage shunt inputs.
TABLE 15. 0xD4 CONFIGURE ICHANNEL REGISTER DEFINITION
BIT
NUMBER D[15:14] D[13:10]
D[9:7]
D[6:3]
D[2:0]
Bit
Name
N/A Aux Shunt Aux Shunt Prim Shunt Prim Shunt
Sample Conversion Sample Conversion
AVG
Time
AVG
Time
Default 00
00 00
11 1
000 0
111
Value
SHUNT VOLTAGE CONVERSION TIME D[9:7], D[2:0]
The Shunt Voltage Conversion Time bits set the acquisition speed
of the ADC when measuring either the primary or auxiliary
voltage shunt channels of the DPM. The primary and auxiliary
V_SHUNT channels have independent timing control bits allowing
for the primary V_SHUNT channel to have a unique acquisition time
with respect to the auxiliary V_SHUNT channel. Table 16 is a list of
the selectable V_SHUNT ADC time settings. The shaded row
indicates the default setting.
TABLE 16. AUXILIARY/ PRIMARY V_SHUNT CONVERSION TIMES DEFINED
Config_Ichannel: D[9:7],D[2:0]
CONVERSION TIME
0
0
0
64µs
0
0
1
128µs
0
1
0
256µs
0
1
1
512µs
1
0
X
1.024ms
1
1
X
2.048ms
SHUNT VOLTAGE SAMPLE AVERAGE D[13:10], D[6:3]
The Shunt Voltage Sample Average bits set the number of
averaging samples for a unique sampling time. The DPM will
record all samples and output the average resultant to the
respective V_SHUNT register. The primary and auxiliary V_SHUNT
channels have independent average settings allowing for the
primary V_SHUNT channel to have a unique average setting with
respect to the auxiliary average setting. Table 17 defines the list
of selectable averages the DPM can be set to. The shaded row
indicates the default setting.
TABLE 17. AUXILIARY/ PRIMARY V_SHUNT NUMBER OF SAMPLES TO
AVERAGE DEFINED
AVG[3:0]
CONVERTER AVERAGES
0000
1
0001
2
0010
4
0011
8
0100
16
0101
32
0110
64
0111
128
1000
256
1001
512
1010
1024
1011
2048
11XX
4096
0X38 IOUT CALIBRATION GAIN (R/W)
The IOUT Calibration Gain register is a read/writable word
register that is used to calculate current and power
measurements for the primary channel of the DPM. When the
register is programmed, the DPM calculates the current and
power based on the primary channels V_BUS and V_SHUNT
measurements. The calculation resultant is stored in the
READ_IOUT and READ_POUT registers.
The calibration register value can be calculated as follows:
1. Calculate the full-scale current range that is desired. This can
be calculated using Equation 3.
Current _FS
Vshunt _FS
R _shunt
(EQ. 3)
2. R_SHUNT is the value of the shunt resistor. Vshunt_FS is the
full-scale range of the primary channel, which equals 80mV.
3. From the current full-scale range, the current LSB can be
calculated using Equation 4. Current full-scale is the outcome
from Equation 3. ADC_res is the resolution of shunt voltage
reading. The output of the ADC is a signed 15-bit binary
number. Therefore, the ADC_res value equals 2¹⁵ or 32768.
Current _LSB
Current _FS
ADC _res
(EQ. 4)
4. From Equation 4, the calibration resistor value can be
calculated using Equation 5. The resolution of the math that
is processed internally in the DPM is 2048 or 11 bits of
resolution. The V_{SHUNT LSB} is set to 2.5µV. Equation 5 yields a
15-bit binary number that can be written to the calibration
register. The calibration register format is represented in
Table 18.
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FN8389.5
March 18, 2016