SI53304 Datasheet, PDF (32/33 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53304
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 1.0
Corrected front-page buffer block diagram.
Improved performance specifications with more
detail.
Added additional information to clarify the use of the
voltage reference feature.
Added pin type description to Table 20, “Pin
Description,” on page 25.
Added low-voltage termination options for 1.2 V and
1.5 V LVCMOS support.
Clarified output clock bank A and bank B
assignments.
32
Rev. 1.0