SI53304 Datasheet, PDF (16/33 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53304
2.7. Input Mux and Output Enable Logic
Two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects
the active clock input. The table below summarizes the input and output clock based on the input mux and output
enable pin settings.
Table 18. Input Mux and Output Enable Logic
CLK_SEL
CLK0
CLK1
OE¹
Q²
L
L
X
H
L
L
H
X
H
H
H
X
L
H
L
H
X
H
H
H
X
X
X
L
L³
Notes:
1. Output enable active high
2. On the next negative transition of CLK0 or CLK1.
3. Single-end: Q = low, Q = low
Differential: Q = low, Q = high
2.8. Power Supply (V_DD and V_DDOX)
The device includes separate core (V_DD) and output driver supplies (V_DDOX). This feature allows the core to
operate at a lower voltage than V_DDO, reducing current consumption in mixed supply applications. The core V_DD
supports 3.3 V, 2.5 V, or 1.8 V. Each output bank has its own V_DDOX supply, supporting 3.3 V, 2.5 V, or 1.8 V.
16
Rev. 1.0