SI53304 Datasheet, PDF(13/33 Page) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

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SI53304 Datasheet, PDF (13/33 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

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Si53304

2.2. Input Bias Resistors

Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.

The non-inverting input is biased with a 18.75 kï pull-down to GND and a 75 kï pull-up to VDD. The inverting input

is biased with a 75 kï pull-up to VDD.

VDD

RPU

RPD

RPU = 75 kï

RPD = 18.75 kï

CLK0 or

CLK1

Figure 5. Input Bias Resistors

2.3. Input Clock Voltage Reference (VREF)

The VREF pin is used to bias the input receiver when a differential input clock is terminated as a single-ended

reference clock to the device. Connect the single-ended input to either CLK0 or CLK1. Use the recommended input

termination and bias circuit as shown in Figure 3. Note that the VREF pin should be left floating when LVCMOS or

differential clocks are used.

CLKx

Si533xx

/ CLKx

100 nF

VREF

Figure 6. Using Voltage Reference with Single-Ended Input Clock

Rev. 1.0

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