SI53304 Datasheet, PDF (14/33 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53304
2.4. Universal, Any-Format Output Buffer
The highly flexible output drivers support a wide range of clock signal formats, including LVPECL, low power
LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUTx[1] and SFOUTx[0] are 3-level inputs that can be pin-
strapped to select the Bank A and Bank B clock signal formats independently. This feature enables the device to be
used for format translation in addition to clock distribution, minimizing the number of unique buffer part numbers
required in a typical application and simplifying design reuse. For EMI reduction applications, four LVCMOS drive
strength options are available for each V_DDO setting.
Table 17. Output Signal Format Selection
SFOUTX[1]
Open*
SFOUTX[0]
Open*
V_DDOX = 3.3 V
LVPECL
V_DDOX = 2.5 V
LVPECL
V_DDOX = 1.8 V
N/A
0
0
LVDS
LVDS
LVDS
0
1
LVCMOS, 24 mA drive LVCMOS, 18 mA drive
LVCMOS, 12 mA drive
1
0
LVCMOS, 18 mA drive LVCMOS, 12 mA drive
LVCMOS, 9 mA drive
1
1
LVCMOS, 12 mA drive LVCMOS, 9 mA drive
LVCMOS, 6 mA drive
Open*
0
LVCMOS, 6 mA drive LVCMOS, 4 mA drive
LVCMOS, 2 mA drive
Open*
1
LVPECL low power
LVPECL low power
N/A
0
Open*
CML
CML
CML
1
Open*
HCSL
N/A
N/A
*Note: SFOUTx are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to V_DD/2.
14
Rev. 1.0