SI53304 Datasheet, PDF (15/33 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53304
2.5. Glitchless Clock Input Switching
The input clock mux features glitchless switching between two valid input clocks. Figure 7 illustrates that switching
between input clocks does not generate runt pulses or glitches at the output.
CLK1
CLK0
CLK_SEL
Qn
Note 1
Note 2
Note 3
Notes:
1. Q_n continues with CLK0 for 2-3 falling edges of CLK0.
2. Q_n is disabled low for 2-3 falling edges of CLK1 .
3. Q_n starts on the first rising edge after 1 + 2.
Figure 7. Glitchless Input Clock Switch
Glitchless switching between 2 input clocks that are up to 10x different in frequency is supported. When a
switchover to a new clock is made, the output will disable low after two or three clock cycles of the previously-
selected input clock. The outputs will remain low for up to three clock cycles of the newly-selected clock, after
which the outputs will start from the newly-selected input. In the case a switchover to an absent clock is made, the
output will glitchlessly stop low and wait for edges of the newly selected clock. A switchover from an absent clock to
a live clock will also be glitchless. Note that the CLK_SEL input should not be toggled faster than 1/250th the
frequency of the slower input clock.
2.6. Synchronous Output Enable
This buffer features a synchronous output enable (disable) feature. Output enable is sampled and synchronized on
the falling edge of the input clock. This feature prevents runt pulses from being generated when the outputs are
enabled or disabled.
When OE is low, Q is held low and Q is held high for differential output formats. For LVCMOS output format
options, both Q and Q are held low when OE is set low. The device outputs are enabled when the output enable pin
is unconnected. See Table 10, “AC Characteristics,” on page 6 for output enable and output disable times.
Rev. 1.0
15