SI53304 Datasheet, PDF (27/33 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53304
Table 20. Pin Description (Continued)
Pin
Name
Type*
Description
19
V_DDOB
P Output voltage supply—Bank B (Outputs: Q3 to Q5)
Bypass with 1.0 µF capacitor and place as close to the V_DDOB pin as
possible.
20
Q5
O Output clock 5 (complement)
21
Q5
O Output clock 5
22
SFOUTB[0]
23
SFOUTB[1]
24
OE5
I Output signal format control pin for Bank B
Three level input control. Internally biased at V_DD/2. Can be left floating
or tied to ground or V_DD.
I Output signal format control pin for Bank B
Three level input control. Internally biased at V_DD/2. Can be left floating
or tied to ground or V_DD.
I Output enable—Output 5
When OE = high, the Q5 is enabled.
When OE = low, Q is held low and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
This pin contains an internal pull-up resistor.
25
Q4
O Output clock 4 (complement)
26
Q4
O Output clock 4
27
Q3
O Output clock 3 (complement)
28
Q3
O Output clock 3
29
Q2
O Output clock 2 (complement)
30
Q2
O Output clock 2
31
Q1
O Output clock 1 (complement)
32
Q1
O Output clock 1
GND
Pad
GND
GND Ground Pad
Power supply ground and thermal relief.
*Pin types are: I = input, O = output, P = power, GND = ground.
Rev. 1.0
27