SI53304 Datasheet, PDF (1/33 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53304
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE
Features
 6 differential or 12 LVCMOS outputs  Independent V_DD and V_DDO:
 Ultra-low additive jitter: 45 fs rms
1.8/2.5/3.3 V
 Wide frequency range: 1 to 725 MHz _{ 1.2/1.5 V LVCMOS output support}
 Any-format input with pin selectable _{ Excellent power supply noise}
output formats: LVPECL, Low Power _{rejection (PSRR)}
LVPECL, LVDS, CML, HCSL,
 Selectable LVCMOS drive strength to
LVCMOS
tailor jitter and EMI performance
 2:1 mux with hot-swappable inputs _{ Small size: 32-QFN (5x5 mm)}
 Glitchless input clock switching
 RoHS compliant, Pb-free
 Synchronous output enable
 Industrial temperature range:
 Individual output enable
–40 to +85 °C
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Description
The Si53304 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53304 features a 2:1 mux with
glitchless switching, making it ideal for redundant clocking applications. The
Si53304 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53304 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments. Independent core and output bank supply pins provide
integrated level translation without the need for external circuitry.
Functional Block Diagram
VREF
Vref
Generator
VDD
Power
Supply
Filtering
VDDOA
SFOUTA[1:0]
OE[2:0]
Ordering Information:
See page 28.
Pin Assignments
Si53304
OE0 1
SFOUTA[1] 2
SFOUTA[0] 3
Q0 ⁴
Q0 5
GND 6
VDD
7
CLK_SEL 8
GND
PAD
24 OE5
23 SFOUTB[1]
22 SFOUT_B[0]
21 Q5
20 Q5
19 VDDOB
18 VDDOA
17 VREF
Patents pending
CLK0
/CLK0
CLK1
/CLK1
CLK_SEL
Switching
Logic
BANK A
VDDOB
SFOUTB[1:0]
OE[5:3]
BANK B
Rev. 1.0 4/14
Copyright © 2014 by Silicon Laboratories
Si53304