SI53304 Datasheet, PDF (26/33 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53304
Pin
Name
8
CLK_SEL
9
OE1
10
CLK0
11
CLK0
12
OE2
13
OE3
14
CLK1
15
CLK1
16
OE4
17
V_REF
18
V_DDOA
Table 20. Pin Description (Continued)
Type*
Description
I Mux input select pin (LVCMOS)
Clock inputs are switched without the introduction of glitches.
When CLK_SEL is high, CLK1 is selected.
When CLK_SEL is low, CLK0 is selected.
CLK_SEL contains an internal pull-down resistor.
I Output enable—Output 1
When OE = high, the Q1 is enabled.
When OE = low, Q is held low and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
This pin contains an internal pull-up resistor.
I Input clock 0
I Input clock 0 (complement)
When the CLK0 is driven by a single-end input, connect CLK0 to V_DD/2.
I Output enable—Output 2
When OE = high, the Q2 is enabled.
When OE = low, Q is held low and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE2 contains an internal pull-up resistor.
I Output enable—Output 3
When OE = high, the Q3 is enabled.
When OE = low, Q is held low and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE3 contains an internal pull-up resistor.
I Input clock 1
I Input clock 1 (complement)
When the CLK1 is driven by a single-end input, connect CLK1 to V_DD/2.
I Output enable—Output 4
When OE = high, the Q4 is enabled.
When OE = low, Q is held low and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
This pin contains an internal pull-up resistor.
O Input clock reference voltage used to bias CLK0 or CLK1 clock input
pins. V_REF is required when a differential input clock is applied to the
device and terminated as a single-ended reference. V_REF may be left
unconnected for LVCMOS or differential clock inputs. See “2.3. Input
Clock Voltage Reference (VREF)” for details.
P Output voltage supply—Bank A (Outputs: Q0 to Q2)
Bypass with 1.0 µF capacitor and place as close to the V_DDOA pin as
possible.
26
Rev. 1.0