SI53304 Datasheet, PDF (25/33 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53304
OE0 1
SFOUTA[1] 2
SFOUTA[0] 3
Q0 ⁴
Q0 5
GND 6
VDD 7
CLK_SEL 8
GND
PAD
24 ^OE5
23 SFOUTB[1]
22 _SFOUTB[0]
21 _Q5
20 _Q5
19 ^VDDOB
18 ^VDDOA
17 VREF
Table 20. Pin Description
Pin
Name
Type*
Description
1
OE0
I Output enable—Output 0
When OE = high, the Q0 is enabled.
When OE = low, Q is held low and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
This pin contains an internal pull-up resistor.
2
SFOUTA[1]
I Output signal format control pin for Bank A
Three level input control. Internally biased at V_DD/2. Can be left floating
or tied to ground or V_DD.
3
SFOUTA[0]
I Output signal format control pin for Bank A
Three level input control. Internally biased at V_DD/2. Can be left floating
or tied to ground or V_DD.
4
Q0
O Output clock 0 (complement)
5
Q0
O Output clock 0
6
GND
O Ground
7
V_DD
P Core voltage supply
Bypass with 1.0 µF capacitor and place as close to the V_DD pin as possi-
ble.
Rev. 1.0
25