SI53340-45 Datasheet, PDF (27/38 Pages) Silicon Laboratories – Multiple configuration options

Si53340-45 Data Sheet
Pin Descriptions
Pin #
Name
Type¹
Description
15
Q7
O
Output clock 7.
16
VDD
P
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as closely to
the VDD pin as possible.
17
Q6b
O
Output clock 6 (complement).
18
Q6
O
Output clock 6.
19
Q5b
O
Output clock 5 (complement).
20
Q5
O
Output clock 5.
21
Q4b
O
Output clock 4 (complement).
22
Q4
O
Output clock 4.
23
Q3b
O
Output clock 3 (complement).
24
Q3
O
Output clock 3.
25
VDD
P
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as closely to
the VDD pin as possible.
26
Q2b
O
Output clock 2 (complement).
27
Q2
O
Output clock 2.
28
Q1b
O
Output clock 1 (complement).
29
Q1
O
Output clock 1.
30
Q0b
O
Output clock 0 (complement).
31
Q0
O
Output clock 0.
32
VDD
P
Core voltage supply. Bypass with 1.0 µF capacitor and place as closely to the VDD pin
as possible.
GND Pad
Exposed
Ground Pad
GND
Power supply ground and thermal relief. The exposed ground pad is thermally connected
to the die to improve the heat transfer out of the package. The ground pad must be con-
nected to GND to ensure device specifications are met.
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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