SI53340-45 Datasheet, PDF (26/38 Pages) Silicon Laboratories – Multiple configuration options

5.3 Si53344/45 Pin Descriptions
VDD 1
CLK_SEL 2
CLK0 3
CLK0b 4
N/C 5
CLK1 6
CLK1b 7
GND 8
GND
PAD
Si53344
32-QFN
24 Q3
23 Q3b
22 Q4
21 Q4b
20 Q5
19 Q5b
18 Q6
17 Q6b
VDD 1
CLK_SEL 2
CLK0 3
N/C ⁴
N/C 5
CLK1 6
N/C ⁷
GND 8
Si53340-45 Data Sheet
Pin Descriptions
GND
PAD
Si53345
32-QFN
24 Q3
23 Q3b
22 Q4
21 Q4b
20 Q5
19 Q5b
18 Q6
17 Q6b
Table 5.3. Si53344/45 32-QFN Pin Descriptions
Pin #
1
Name
VDD
2
CLK_SEL
3
CLK0
CLK0b
(Si53344 only)
4
NC
(Si53345 only)
5
NC
6
CLK1
CLK1b
(Si53344 only)
7
NC
(Si53345 only)
8
GND
9
VDD
10
Q9b
11
Q9
12
Q8b
13
Q8
14
Q7b
Type¹
P
I
I
I
—
Description
Core and Output voltage supply. Bypass with 1.0 μF capacitor and place as close to the
VDD pin as possible.
Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When
CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
Input clock 0.
Input clock 0 (complement). When CLK0 is driven by a single-ended LVCMOS input,
connect CLK0b to an appropriate bias voltage (e.g., V_DD/2.
No connect. Leave this pin unconnected.
No connect. Leave this pin unconnected.
I
Input clock 1.
I
Input clock 1 (complement). When CLK1 is driven by a single-ended LVCMOS input,
connect CLK1b to an appropriate bias voltage (e.g., V_DD/2.
—
No connect. Leave this pin unconnected.
GND
P
O
O
O
O
O
Ground.
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as closely to
the VDD pin as possible.
Output clock 9 (complement).
Output clock 9.
Output clock 8 (complement).
Output clock 8.
Output clock 7 (complement).
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