SI53340-45 Datasheet, PDF (16/38 Pages) Silicon Laboratories – Multiple configuration options

Si53340-45 Data Sheet
Electrical Specifications
Table 3.4. Output Characteristics (LVDS)
V_DD = 1.8 V, 2.5 V, or 3.3 V; T_A = –40 to 85 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Output Swing¹
V_SE
R_L = 100 Ω across Q_N and Qb_N
200
—
490
mV
Output Common Mode Voltage
(V_DD = 2.5 or 3.3 V)
V_COM1
V_DD = 2.38 to 2.63 V, 2.97 to 3.63 V,
R_L = 100 Ω across Q_N and Qb_N
1.10
1.25
1.35
V
Output Common Mode Voltage
(V_DD = 1.8 V)
V_COM2
V_DD = 1.71 to 1.89 V,
0.83
0.97
1.25
V
R_L = 100 Ω across Q_N and Qb_N
Note:
1. Unused outputs can be left floating. Do not short unused outputs to ground.
Table 3.5. AC Characteristics
V_DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ±10%; T_A = –40 to 85 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency
F
Si53341/43/45
Si53340/42/44
dc
—
200
MHz
dc
—
1250
MHz
Duty Cycle
(50% input duty cycle)
20/80% T_R/T_F<10% of period
Differential input clock
47
50
53
%
D_C
20/80% T_R/T_F<10% of period
45
50
55
%
(Single-ended input clock)
SR_diff
Required to meet prop delay and ad-
ditive jitter specifications (20–80%)
0.75
—
Minimum Input Clock Slew Rate
SR_se
Required to meet prop delay and ad- 1.00
—
ditive jitter specifications (20–80%)
—
V/ns
—
V/ns
Output Rise/Fall Time
T_R/T_F
20-80%
—
—
350
ps
Minimum Input Pulse Width
T_W
360
—
—
ps
Propagation Delay
T_PLH, T_PHL
650
850
1050
ns
Output-to-Output Skew¹
T_SK
—
—
50
ps
Part-to-Part Skew²
T_PS
—
—
125
ps
10 kHz sinusoidal noise
—
–70
—
dBc
Power Supply Noise Rejection³
PSRR
100 kHz sinusoidal noise
500 kHz sinusoidal noise
—
–65
—
dBc
—
–60
—
dBc
1 MHz sinusoidal noise
—
–57.5
—
dBc
Note:
1. Output-to-output skew specified for outputs with identical configuration.
2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load con-
dition. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DD (3.3 V = 100 mV_PP) and noise spur amplitude meas-
ured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for more information.
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