SI53340-45 Datasheet, PDF (13/38 Pages) Silicon Laboratories – Multiple configuration options

Si53340-45 Data Sheet
Functional Description
2.9 Input Mux Noise Isolation
The input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase jitter performance when
clocks are present at both the CLK0 and CLK1 inputs. The following figure shows a measurement of the input mux’s noise isolation.
Figure 2.13. Input Mux Noise Isolation (Differential Input Clock, 44-QFN Package)
Figure 2.14. Input Mux Noise Isolation (Single-Ended Input Clock, 24-QFN Package)
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