SI53340-45 Datasheet, PDF (24/38 Pages) Silicon Laboratories – Multiple configuration options

5.2 Si53342/43 Pin Descriptions
Si53340-45 Data Sheet
Pin Descriptions
OEAb 1
Q1b 2
Q1 3
Q0b 4
Q0 5
VDD 6
GND
PAD
Si53342
24-QFN
18 OEBb
17 Q4
16 Q4b
15 Q5
14 Q5b
13 CLK_SEL
OEAb 1
Q1b 2
Q1 3
Q0b 4
Q0 5
VDD 6
GND
PAD
Si53343
24-QFN
18 OEBb
17 Q4
16 Q4b
15 Q5
14 Q5b
13 CLK_SEL
Table 5.2. Si53342/43 24-QFN Pin Descriptions
Pin
Name
Type¹
Description
1
OEAb
I
Output Enable for Bank A (Q0, Q1, Q2). When OEAb = LOW, outputs Q0, Q1, and Q2
are enabled. This pin contains an active pull-down resistor, and leaving the pin discon-
nected enables the outputs. When OEAb = HIGH, Q0, Q1, and Q2 are disabled.
2
Q1b
O
Output clock 1 (complement).
3
Q1
O
Output clock 1.
4
Q0b
O
Output clock 0 (complement)
5
Q0
O
Output clock 0
6
VDD
P
Core voltage supply. Bypass with 1.0 μF capacitor and place as close to the VDD pin as
possible.
7
CLK0
I
Input clock 0.
8
CLK0b
(Si53342 only)
O
Input clock 0 (complement). When CLK0 is driven by a single-ended LVCMOS input,
connect CLK0b to an appropriate bias voltage (e.g., V_DD/2.
NC
(Si53343 only)
—
No connect. Leave this pin unconnected.
9
NC
—
No Connect. Do not connect this pin to anything.
10
NC
—
No Connect. Do not connect this pin to anything.
11
CLK1
I
Input clock 1.
12
CLK1b
(Si53342 only)
I
Input clock 1 (complement). When CLK1 is driven by a single-ended LVCMOS input,
connect CLK1b to an appropriate bias voltage (e.g., V_DD/2.
NC
(Si53343 only)
—
No connect. Leave this pin unconnected.
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