SI53340-45 Datasheet, PDF (10/38 Pages) Silicon Laboratories – Multiple configuration options

Si53340-45 Data Sheet
Functional Description
2.7 Typical Phase Noise Performance: Differential Input Clock
Each of the three phase noise plots superimposes Source Jitter, Total SE Jitter and Total Diff Jitter on the same diagram.
• Source Jitter—Reference clock phase noise (measured Single-ended to PNA).
• Total Jitter (SE)—Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer
and integrated from 12 kHz to 20 MHz.
• Total Jitter (Diff)—Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer
and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. For more infor-
mation, see 3. Electrical Specifications.
Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS).
CLK SYNTH
SMA103A
CLKx
Si5334x
DUT
Total jitter
measured here
AG E5052 Phase Noise
Analyzer
50
50 Ohm
Source jitter
measured here
Figure 2.8. Differential Measurement Method Using a Balun
The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calcula-
ted (via root-sum-square addition).
Frequency
Differential
Source Jitter
(MHz) Input Slew Rate (V/ns)
(fs)
156.25
1.0
38.2
Total Jitter
(SE) (fs)
147.8
Additive Jitter
(SE) (fs)
142.8
Total Jitter
(Differential) (fs)
118.3
Additive Jitter
(Differential) (fs)
112.0
Figure 2.9. Total Jitter Differential Input (156.25 MHz)
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