SI53340-45 Datasheet, PDF (25/38 Pages) Silicon Laboratories – Multiple configuration options

Si53340-45 Data Sheet
Pin Descriptions
Pin
Name
Type¹
Description
13
CLK_SEL
I
Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When
CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
14
Q5b
O
Output clock 5 (complement).
15
Q5
O
Output clock 5.
16
Q4b
O
Output clock 4 (complement).
17
Q4
O
Output clock 4.
18
OEBb
I
Output Enable for Bank B (Q3, Q4, Q5). When OEBb = LOW, outputs Q3, Q4, and Q5
are enabled. This pin contains an active pull-down resistor, and leaving the pin discon-
nected enables the outputs. When OEBb = HIGH, Q3, Q4, and Q5 are disabled.
19
VDDOB
P
Output voltage spply—Bank B (Outputs: Q3 to Q5). Bypass with 1.0 µF capacitor and
place as close to the VDDOB pin as possible.
20
Q3b
O
Output clock 3 (complement).
21
Q3
O
Output clock 3.
22
Q2b
O
Output clock 2 (complement).
23
Q2
O
Output clock 2.
24
VDDOA
P
Output voltage supply—Bank A (Outputs: Q0 to Q2). Bypass with 1.0 μF capacitor and
place as close to the VDDOA pin as possible.
GND Pad
Exposed
Ground Pad
GND
Power supply ground and thermal relief. The exposed ground pad is thermally connected
to the die to improve heat transfer from the package. The ground pad must be connected
to GND to ensure device specifications are met.
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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