SI53340-45 Datasheet, PDF (22/38 Pages) Silicon Laboratories – Multiple configuration options

5. Pin Descriptions
5.1 Si53340/41 Pin Descriptions
Si53340-45 Data Sheet
Pin Descriptions
GND ¹
CLK_SEL 2
CLK1 3
CLK1b 4
GND
PAD
Si53340
16-QFN
12 _Q1b
11 _Q1
10 _Q0b
9 _Q0
GND ¹
CLK_SEL 2
CLK1 3
NC 4
GND
PAD
Si53341
16-QFN
12 _Q1b
11 _Q1
10 _Q0b
9 _Q0
Table 5.1. Si53340/41 16-QFN Pin Descriptions
Pin
Name
Type¹
Description
1
GND
GND
Ground.
2
CLK_SEL
I
Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When
CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
3
CLK1
I
Input clock 1.
CLK1b
(Si53340 only)
4
NC
(Si53341 only)
I
Input clock 1 (complement). When CLK1 is driven by a single-ended LVCMOS input,
connect CLK1b to an appropriate bias voltage (e.g., V_DD/2.
—
No connect. Leave this pin unconnected.
5
VDD
P
Core and Output Voltage Supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
6
CLK0
I
Input Clock 0.
CLK0b
(Si53340 only)
7
NC
(Si53341 only)
I
Input clock 0 (complement). When CLK0 is driven by a single-ended LVCMOS input,
connect CLK0b to an appropriate bias voltage (e.g., V_DD/2.
—
No connect. Leave this pin unconnected.
8
NC
—
No connect. Do not connect this pin.
9
Q0
O
Output clock 0.
10
Q0b
O
Output clock 0 (complement).
11
Q1
O
Output clock 1.
12
Q1b
O
Output clock 1 (complement).
13
Q2
O
Output clock 2.
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