SI8261AAC-C-IS Datasheet, PDF (18/40 Pages) Silicon Laboratories – 5 KV LED EMULATOR INPUT, 4.0 A ISOLATED GATE DRIVERS

Si826x
Consequently, opto coupler circuits using this technique should either leave the negative bias circuitry unpopulated
or modify the circuitry (e.g., add a clamp diode or current limiting resistor) to ensure that the anode pin of the
Si826x is no more than –0.3 V with respect to the cathode when reverse-biased.
New designs should consider the input circuit configurations of Figure 16, which are more efficient than those of
Figures 14 and 15. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOSFET, analog
transmission gate, processor I/O, etc. Also, note that the Si826x input can be driven from the I/O port of any MCU
or FPGA capable of sourcing a minimum of 6 mA (see Figure 16C). Additionally, note that the Si826x propagation
delay and output drive do not significantly change for values of I_F between I_F(MIN) and I_F(MAX).
Vext
R1
Control
Input
S1
See Text
Si826x
1 _N/C
2 _ANODE
Vext
S1
Control
Input
R1
3 CATHODE
S2
4 _N/C
A
Si826x
1 ^N/C
2 ANODE
3 ^CATHODE
4 _N/C
B
Si826x
1 N/C
MCU I/O
Port pin
2 ANODE
R1
3 CATHODE
4 N/C
C
Figure 16. Si826x Other Input Circuit Configurations
5.2. Output Circuit Design
GND can be biased at, above, or below ground as long as the voltage on V_DD with respect to GND is a maximum
of 30 V. V_DD decoupling capacitors should be placed as close to the package pins as possible. The optimum
values for these capacitors depend on load current and the distance between the chip and its power source. It is
recommended that 0.1 and 10 µF bypass capacitors be used to reduce high-frequency noise and maximize
performance.
5.3. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the V_DD lines. Care must be taken to
minimize parasitic inductance in these paths by locating the Si826x as close as possible to the device it is driving.
In addition, the V_DD supply and ground trace paths must be kept short. For this reason, the use of power and
ground planes is highly recommended. A split ground plane system having separate ground and V_DD planes for
power devices and small signal components provides the best overall noise performance.
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Rev. 1.3